Deming Zhang

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron

Artificial synaptic devices implemented by emerging post-CMOS non-volatile memory technologies such as Resistive RAM (RRAM) have made great progress recently. However, it is still a big challenge to fabricate stable and controllable multilevel RRAM. Benefitting from the control of electron spin instead of electron charge, spintronic devices, e.g., magnetic tunnel junction (MTJ) as a binary device, have been explored for neuromorphic computing with low power dissipation. In this paper, a compound spintronic device consisting of multiple vertically stacked MTJs is proposed to jointly behave as a synaptic device, termed as compound spintronic synapse (CSS). Based on our theoretical and experimental work, it has been demonstrated that the proposed compound spintronic device can achieve designable and stable multiple resistance states by interfacial and materials engineering of its components. Additionally, a compound spintronic neuron (CSN) circuit based on the proposed compound spintronic device is presented, enabling a multi-step transfer function. Then, an All Spin Artificial Neural Network (ASANN) is constructed with the CSS and CSN circuit. By conducting system-level simulations on the MNIST database for handwritten digital recognition, the performance of such ASANN has been investigated. Moreover, the impact of the resolution of both the CSS and CSN and device variation on the system performance are discussed in this work.

Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning

Recently, magnetic tunnel junction with in-plane magnetization (i-MTJ) has been exploited to behave as a binary stochastic synapse. However, it suffers from its limited level of synaptic weight, resulting in an inaccurate learning. In this work, a compound synapse that employs multiple perpendicular MTJs (p-MTJs) in series is proposed. It possesses an analog-like synaptic weight under weak programming conditions, which leads to a stochastic learning rule and low power consumption per synaptic event. By performing system-level simulations on the MNIST database, it has been demonstrated that such compound spin synapses can realize stochastic neuromorphic computation with high accuracy and low energy consumption.

Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation

Spintronics devices such as magnetic tunnel junction (MTJ) have been investigated for the neuromorphic computation. However, there are still a number of challenges for hardware implementation of the bio-inspired computing, for instance how to use the binary MTJ to mimic the analog synapse. In this paper, a compound scheme is firstly proposed, which employs multiple MTJs connected in parallel operating in the stochastic regime to jointly behave a single synapse, aiming to achieve an analog-like weight spectrum. To further exploit its stochastic switching property for the bio-inspired computing, we present a MTJ based stochastic spiking neuron (SSN) circuit, which can also realize the neural rate coding scheme. A case study is made on the MNIST database for handwritten digital recognition with the proposed compound magnetoresistive synapse (CMS) and SSN. System-level simulation results show that the proposed CMS and SSN can implement neuromorphic computation with high accuracy and immunity to device variation.

High-Speed, Low-Power, and Error-Free Asynchronous Write Circuit for STT-MRAM and Logic

Benefiting from its simple switching scheme (only a bidirectional current source), high-speed and low-power spin-transfer torque (STT) has been regarded as one of the most promising switching mechanisms for a magnetic tunnel junction (MTJ)-based non-volatile memory and logic circuits. However, it suffers from a number of reliability issues like write error induced by its intrinsic stochasticity, process variation, and so on. In order to reduce the write error rate, the mainstream solution is to enlarge the write pulse duration at the expense of write energy dissipation. Some self-terminated write circuits have been proposed to avoid the wasted write energy. But the hardware cost of these write circuits is especially large. In this paper, a novel cost-efficient self-terminated write circuit is proposed using two simple built-in sensing circuits. The proposed write circuit is simulated with a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit. The simulation result shows about 35% reduction of circuit area and 10% lower energy consumption in comparison with that in prior work. In addition, the Error-Free write operation under process variation of both the CMOS transistor and the STT-MTJ is achieved due to its large sense margin (~320 mV).

Heterogeneous Memristive Devices Enabled by Magnetic Tunnel Junction Nanopillars Surrounded by Resistive Silicon Switches

Emerging non-volatile memories (NVMs) have currently attracted great interest for their potential applications in advanced low-power information storage and processing technologies. Conventional NVMs, such as magnetic random access memory (MRAM) and resistive random access memory (RRAM) suffer from limitations of low tunnel magnetoresistance (TMR), low access speed or finite endurance. NVMs with synergetic advantages are still highly desired for future computer architectures. Here, we report a heterogeneous memristive device composed of a magnetic tunnel junction (MTJ) nanopillar surrounded by resistive silicon switches, named resistively enhanced MTJ (Re-MTJ), that may be utilized for novel memristive memories, enabling new functionalities that are inaccessible for conventional NVMs. The Re-MTJ device features a high ON/OFF ratio of >1000% and multilevel resistance behaviour by combining magnetic switching together with resistive switching mechanisms. The magnetic switching originates from the MTJ, while the resistive switching is induced by a point-switching filament process that is related to the mobile oxygen ions. Microscopic evidence of silicon aggregated as nanocrystals along the 2 edges of the nanopillars verifies the synergetic mechanism of the heterogeneous memristive device. This device may provide new possibilities for advanced memristive memory and computing architectures, e.g., in-memory computing and neuromorphics.

Spin wave based synapse and neuron for ultra low power neuromorphic computation system

In this work, we have proposed that the neural synapses and neurons can be realized by utilizing spin waves (SWs) as information carrier. The SWs is excited by spin torque nano-oscillator (STNO), and detected with several different physical mechanisms: 1) tunneling magnetic-resistance 2) spin pumping and 3) inverse spin hall effect. The proposed SWs based synapses and neurons can be further combined together to form a neuromorphic computation system with crossbar structure. Possible ultra low power consumption and ultra high speed are the advantage of our proposed SWs based synapses and neurons.

A novel SEU-tolerant MRAM latch circuit based on C-element

Benefiting from its inherent hardness to radiation and non-volatility, magnetic random access memory (MRAM) is considered as one of the most promising non-volatile memory (NVM) technologies for aerospace and avionic electronics. However, MRAM is still sensitive to single event upsets (SEU) due to its CMOS employed peripheral circuit. In this paper, we propose a novel SEU-tolerant MRAM latch circuit, which is based on the special device C-element. By using a physics-based MTJ compact model and the 40nm design kit, hybrid simulations have been performed and simulation results show that the proposed MRAM latch circuit is immune to radiation effects.

Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect

In this work, a novel Spin Torque Nano Oscillator (STNO) device which can sustain high frequency oscillation without demand of bias magnetic field is proposed. Voltage Controlled Magnetic Anisotropy (VCMA) effect is employed to increase perpendicular anisotropy field leading to high oscillation frequency in the absence of bias magnetic field. In addition, VCMA effect also can be utilized as frequency modulation approach to realize signal modulation for STNO used in communication system.

High speed low power all spin logic devices assisted by negative capacitance amplified voltage controlled magnetic anisotropy effect

In this paper, we propose an all spin logic device with voltage controlled magnetic anisotropy (VCMA-ASL) and employ negative capacitance (NC) effect as a novel approach to amplify the VCMA effect. A new working strategy of 3-step operation scheme has been proposed, which reduces the energy consumption effectively as well as accelerates switching process.

Reliability-enhanced hybrid CMOS/MTJ logic circuits

Benefitting from its non-volatility, low power, high speed, nearly infinite endurance, good scalability and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in todays programmable logic circuits, which is envisioned to extend the Moores law [1].