Denis Amparo

20

Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA/cm2 Nb/AlOx/Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoNx resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 mum; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of rapid single flux quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of plusmn13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.

{\hbox{kA/cm}}^{2}

It has been found that the critical current of Josephson junctions in superconducting integrated circuits may depend on the environment surrounding the junctions and on how a particular junction is connected (wired) to other junctions and circuit elements. This may cause large, pattern-dependent deviations of the junctions’ critical currents from design values and ultimately limit the yield and performance of superconducting digital integrated circuits. In particular, we have found a difference in the critical current of grounded and floating junctions, and a dependence of the critical current on the size of metal structures connected to the junction—the ‘antenna’ effect. Experimental data were obtained for Nb/AlOx /Nb Josephson junctions fabricated on 150 mm wafers by an 11-layer process for superconducting integrated circuits. The results are explained by plasma process-induced damage to ultra-thin tunnel barriers. The most damaging plasma processing fabrication steps are discussed. (Some figures in this article are in colour only in the electronic version)

Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

It is shown that the critical current density, jc of Nb/AlOx/Nb Josephson junctions in multilayered structures such as superconductor integrated circuits depends on the junction environment and on which wiring layers make contacts to the junction electrodes, and at which stage of the fabrication process. In particular, it is shown that contact holes between the junction base electrode layer and Nb ground plane layer in proximity to the junctions increase their jc and degrade the junction quality. This effect alone may induce enough variation in the properties of Josephson junctions in superconductor integrated circuits to significantly reduce margin of operation and yield of complex circuits. Numerous test structures have been designed, fabricated at various technological regimes, and exhaustively tested in order to investigate various phenomena leading to damage of tunnel barrier or local variation of jc in Nb/Al/AlOx/Nb junctions. The results indicate that layer-dependent and local environment effects on jc are mainly due to electromigration and interlayer diffusion of impurity (hydrogen) atoms around contacts between different layers and changes in hydrogen concentration brought about by wafer processing. Based on the gained insight into the materials science of the phenomenon, methods for minimization and prevention of process-induced changes to Nb/Al/AlOx/Nb tunnel junctions have been developed.

Plasma process-induced damage to Josephson tunnel junctions in superconducting integrated circuits

The effect of dc electrical stress and breakdown on Josephson and quasiparticle tunneling in Nb/Al/AlOx/Nb junctions with ultrathin AlOx barriers typical for applications in superconductor digital electronics has been investigated. The junctions’ conductance at room temperature and current-voltage (I-V) characteristics at 4.2 K have been measured after the consecutive stressing of the tunnel barrier at room temperature. Electrical stress was applied using current ramps with increasing amplitude ranging from 0 to ∼1000Ic corresponding to voltages across the barrier up to ∼0.65 V, where Ic is the Josephson critical current. A very soft breakdown has been observed with polarity-dependent breakdown current (voltage). As the stressing progresses, a dramatic increase in subgap conductance of the junctions, the appearance of subharmonic current steps, and a gradual increase in both the critical and the excess currents as well as a decrease in the normal-state resistance have been observed. The observed changes i...

Process-Induced Variability of

We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.

{\rm Nb/Al}/{\rm AlO}_{\rm x}/{\rm Nb}

The correct operation and high performance of complex superconducting integrated circuits significantly depend on fabrication-process-induced variations of the Josephson junction critical current Ic. Such variations in Nb/Al/AlOx/Nb junctions were investigated and shown to be dependent on how the junction electrodes are connected to other layers in the integrated circuit, especially the ground plane and the Ti/Pd/Au contact pad. The observed enhancement of Ic and gap voltage over time for junctions with certain wiring connections suggests that the phenomenon is related to the diffusion over time of impurities between the junction electrode and the Ti/Pd/Au pad. Considering the strong affinity of both Nb and Ti to H, a model where H is the main impurity element involved in the diffusion-related phenomenon is presented. The results show that direct wiring to Ti is sufficient to observe Ic variations. The results also suggest that as fabricated, the interface between the junction counter-electrode and the AlOx barrier is already close to or at full H saturation, significantly depressing the Ic by up to 20%, compared to clean Nb junctions.

Junctions in Superconductor Integrated Circuits and Protection Against It

Many applications of Nb/Al-AlO_x/Nb Josephson junctions (JJs) in superconducting electronics require high-quality tunnel barriers with low subgap leakage that is usually characterized by figure of merit V_m = I_c R_sg, where I_c is the critical current and R_sg is the subgap resistance at 2 mV and 4.2 K. It is widely believed, and there is considerable literature suggesting, that quality and reproducibility of JJs critically depend on the intrinsic stress in Nb/Al-AlO_x/Nb trilayers, and the stress therefore should be carefully minimized and controlled. Contrary to this belief, we show that JJ quality V_m and reproducibility do not depend on the stress in the trilayer, at least in the studied range from -300 to 300 MPa. In this range, V_m depends neither on the stress in a Nb/Al base electrode nor in a Nb counter electrode. We have found, however, that V_m crucially depends on the way the tunnel barrier formation by thermal oxidation of Al is done. For instance, room-temperature dynamic oxidation (in O₂ flow at low pressures) in a cryopumped chamber leads to poor run-to-run reproducibility of V_m and reduced V_m values, whereas dynamic oxidation at the same parameters but in a chamber with a turbomolecular pump results in high V_m values and excellent run-to-run reproducibility.

Electrical stress effect on Josephson tunneling through ultrathin AlOx barrier in Nb/Al/AlOx/Nb junctions

Superconductor (SC) integrated circuits have several inherent advantages including low power, high speed, and fractional flux quantum sensitivity that can be exploited to achieve discriminating performance for several niche applications in the high-speed computing and radio frequency domain. Despite its several advantages, scaling of SC circuits to higher complexity has been inhibited by the poor circuit yield. One of the critical factors limiting the yield is the poor simulation model to hardware correlation. The current simulation tools for SC circuits such as PSCAN are inadequate to simulate high circuit complexity and do not account for the variations in the fabrication process. To overcome this limitation, we have developed an advanced infrastructure for SC circuit simulation, verification, and model-to-hardware correlation based on the Cadence design suite, particularly using the state-of-the-art Spectre simulator that supports high circuit complexity and Monte Carlo simulations. An improved model-to-hardware correlation will result in several benefits that include enabling circuit scaling to higher complexity. Statistical distributions for critical circuit elements are measured by novel diagnostic circuits that enable measuring multiple instances on a single chip and mimic layout features in actual circuits. Statistical variations are being measured over multiple wafer runs and will be fed into the new simulation infrastructure to achieve better optimization of a complex SC circuit. Furthermore, ring oscillator test circuits for Josephson transmission line have been designed and measured to study the delay per junction as a function of characteristic voltage Vc.

Planarized, Extendible, Multilayer Fabrication Process for Superconducting Electronics

We address all round development of the standard cell library including simulation, layout, and testing. We present a new circuit analysis scheme based on Monte-Carlo simulations and process corners. Using a phase modulation decoder as an example circuit, we identify weak spots in the design that was originally optimized for parameter margins. To support static timing analysis for very high complexity circuits, we describe the timing characterization of library cells as a function of its load, and demonstrate digital timing verification with timing back-annotation using Verilog hardware descriptive language. For the layout of library cells, we present architecture for the dual RSFQ/ERSFQ standard cell library for the MIT-LL, 10 kA/cm2, SFQ4EE and SFQ5EE processes. Testing and characterizing hundreds of library cells, including unique cells and their layout variations, is a challenge. For efficient characterization of the digital cells, we have developed an NDRO cell-based multiplexing scheme that lets us characterize hundreds of cells on a single chip. For better model-to-hardware correlation, we have implemented a differential delay measurement scheme using ring oscillators that facilitates timing characterization of the synchronous and asynchronous cells. We also report design and measurement of statistical variations for the critical current of decision-making pair of junctions.

Investigation of the Role of H in Fabrication-Process- Induced Variations of

Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRESs and MIT-LLs 10-kA/cm² fabrication processes and tested at low (∼kHz) and high (∼GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/–4% to over +/–19% when the Josephson junction count in the FJTL was increased to ∼30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.