Alex F. Kirichenko

20

Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA/cm2 Nb/AlOx/Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoNx resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 mum; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of rapid single flux quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of plusmn13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.

{\hbox{kA/cm}}^{2}

We have developed an advanced version of on-chip test system with new high-speed clock generation and control. For high-speed clock generation, a novel wide-bandwidth ring generator is designed using circular Josephson transmission lines with an inductively coupled trigger. The generator is capable of producing SFQ clock pulses in the range of from 15 to 55 GHz using a 1 kA/cm/sup 2/ Nb fabrication process. For clock control, we have designed two different types of clock-controller circuits based on programmable shift-register and counter. Using the on-chip test system, we have successfully tested a parallel multiplier module up to 15 GHz with 16% dc bias margins.

Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

This paper presents the development of an Analog-to-Digital Converter (ADC) based on a low-temperature superconductor (Nb) chip and room-temperature interface modules for applications in digital receivers for communications, radars, and electronic warfare. The ADC design, MATLAB/sup TM/ simulations, and experimental results of single- and two-tone tests are described.

Advanced on-chip test technology for RSFQ circuits

HYPRES has developed a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering. Detailed experimental results at 20 GHz clock frequency of the ADC chip fabricated with a 1 kA/cm2 Nb process are presented and discussed. In addition to the standard ADC configuration, different ADC modifications are described. In the multi-rate ADC, the modulator sampling frequency is the twice the clock frequency for the time-interleaved digital filter. In addition to the standard parallel-output ADC, a serial output ADC and its interface to room temperature electronics are developed. This serial ADC chip fabricated with the advanced HYPRES 4.5 kA/cm2 process operated up to 34 GHz clock. As a major step toward commercialization of superconducting electronics, an ADC chip was successfully packaged on a cryocooler where it showed reduced performance up to 11.52 GHz clock.

A superconductor high-resolution ADC

There is a desire to move current state-of-the-art niobium Josephson IC fabrication processes (/spl sim/3 /spl mu/m) to smaller sub-micron linewidths in order to realize a decrease in gate size and increase in both speed and packing density. However, cost and time dictates that a way be found to reuse the existing RSFQ gate/cell development that has been done at the 3-/spl mu/m level. Cell retargeting is the process of migrating existing designs to a new technology, with the effort focused on the maximum reuse of existing material. We have investigated a number of issues critical to this process, including both the physical and electrical aspects. Comments are made on methodologies for RSFQ cell retargeting with respect to existing reduced-linewidth JJ fabrication processes. Experimental demonstrations are shown for retargeted RSFQ static digital frequency dividers (toggle flip-flops) operating at 220 GHz, 240 GHz, and 395 GHz.

Superconducting High-Resolution Low-Pass Analog-to-Digital Converters

It has been found that the critical current of Josephson junctions in superconducting integrated circuits may depend on the environment surrounding the junctions and on how a particular junction is connected (wired) to other junctions and circuit elements. This may cause large, pattern-dependent deviations of the junctions’ critical currents from design values and ultimately limit the yield and performance of superconducting digital integrated circuits. In particular, we have found a difference in the critical current of grounded and floating junctions, and a dependence of the critical current on the size of metal structures connected to the junction—the ‘antenna’ effect. Experimental data were obtained for Nb/AlOx /Nb Josephson junctions fabricated on 150 mm wafers by an 11-layer process for superconducting integrated circuits. The results are explained by plasma process-induced damage to ultra-thin tunnel barriers. The most damaging plasma processing fabrication steps are discussed. (Some figures in this article are in colour only in the electronic version)

Retargeting RSFQ cells to a submicron fabrication process

We present the quasi-static and dynamic switching characteristics of orthogonal spin-transfer devices incorporating an out-of-plane magnetized polarizing layer and an in-plane magnetized spin valve device at cryogenic temperatures. Switching at 12 K between parallel and anti-parallel spin-valve states is investigated for slowly varied current as well as for current pulses with durations as short as 200 ps. We demonstrate 100% switching probability with current pulses 0.6 ns in duration. We also present a switching probability diagram that summarizes device switching operation under a variety of pulse durations, amplitudes, and polarities.

Plasma process-induced damage to Josephson tunnel junctions in superconducting integrated circuits

In this paper we present an overview of a family of Time-to-Digital Converter (TDC) systems developed at HYPRES over the past several years. We have developed three types of RSFQ-based time digitizing systems: an eight-channel multi-hit 30-ps TDC, a two-channel multi-hit 6-ps TDC, and a dual-function multi-hit TDC/ADC. We present results of successful testing of an all-digital TDC up to 33-GHz clock frequency, digitizing at 30-ps time intervals. The eight-channel all-digital TDC chip occupies a 1 cm /spl times/1 cm area with more than 10000 Josephson junctions. For better time resolution, the digital counter-based TDC can be integrated with an analog prescaler. The prescaler improves time resolution to 6 ps and has also been successfully tested. We have also integrated TDC channel with sensitive SQUID to a dual-function ADC/TDC digitizer. An advanced VXI-based interface allows the parallel 8-channel data to be acquired at a read-out clock rate of 100 MHz.

Spin-transfer switching of orthogonal spin-valve devices at cryogenic temperatures

We have developed and experimentally demonstrated several new RSFQ circuits, designed as components for digital receivers that are being developed by HYPRES. The first circuit is a digital phase generator, which produces a periodic digital signal with a controllable phase shift. This signal is obtained by decimation of an external high frequency signal by a factor of 1024, and provides a controllable phase shift with digital precision of /spl pi//512. The second circuit, a precise digital static frequency divider, is capable of dividing of an input signal frequency by any integer value between 1 and 1024. The third circuit is a digital quadrature mixer performing digital downconversion of bit-stream data. This report presents results of experimental evaluation of these circuits at speeds in excess of 30 GHz.

Multi-channel time digitizing systems

We have developed a high-performance time digitizer system using a superconductor technology for high-energy and nuclear physics detector instrumentation, CMOS chip diagnostics, and military applications. The system consists of an 8-channel, RSFQ multi-hit Time-to-Digital Converter (TDC) integrated into a single system with a semiconductor VXI interface and control modules. The Digitizer operation and output digital data analysis are performed and fully controlled using custom PC-based LabVIEW/sup TM/ software. This all-digital TDC contains eight 9-hit, 14-bit, 20-GHz TDC channels on a 1 cm /spl times/1 cm chip. The TDC chip is capable of operation in Common Start and Common Stop modes. The VXI digitizer part comprises a 200 MS/s, 8-channel data receiver module, a TDC control module, and a commercial VXI-PCI link. The data receiver module converts data into ECL format. The TDC control module based on Xilinx CPLD technology sorts this data and also controls the superconductive RSFQ chip operation by producing all necessary control and readout signals. We present results of operation and experimental performance evaluation of this system.