Dennis Øland Larsen

High-voltage pulse-triggered SR latch level-shifter design considerations

This paper compares pulse-triggered level shifters with a traditional level-triggered topology for high-voltage applications with supply voltages in the 50 V to 100 V range. It is found that the pulse-triggered SR (Set/Reset) latch level-shifter has a superior power consumption of 1800 μW/MHz translating a signal from 0-3.3 V to 87.5-100 V. The operation of this level-shifter is verified with measurements on a fabricated chip. The shortcomings of the implemented level-shifter in terms of power dissipation, transition delay, area, and startup behavior are then considered and an improved circuit is suggested which has been designed in three variants being able to translate the low-voltage 0-3.3 V signal to 45-50 V, 85-90 V, and 95-100 V respectively. The improved 95-100 V level shifter achieves a considerably lower power consumption of 438 μW/MHz along with a significantly lower transition delay. The 45-50 V version achieves 47.5 μW/MHz and a transition delay of only 2.03 ns resulting in an impressive FOM of 2.03ns/(0.35 μm 50 V) = 0.12ns/μmV.

Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a new dual loop topology. The regulator utilizes the feedback loops to satisfy the challenges for hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0–100 pF capacitive load. The design has been implemented in a 0.18 μm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from 1.0 V–1.4 V supply. A current step load from 250–500 μA with an edge time (rise and fall time) of 1 ns results at ΔVOut of 64 mV with a settling time of 3 μs when CL =0. The power supply rejection ratio (PSRR) at 1 kHz is 63 dB.

Integrated differential high-voltage transmitting circuit for CMUTs

In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption at the scanner operation conditions is 0.754mW without the transducer load and 0.936mW with it.

Integrated differential three-level high-voltage pulser output stage for CMUTs

A new integrated differential three-level high-voltage pulser output stage to drive capacitive micromachined ultrasonic transducers (CMUTs) is proposed in this paper. A topology comparison between the new differential output stage and the most commonly used single-ended topology is performed in order to assess the performance of the new output stage. The new topology achieves a 10.9% lower power consumption and an area reduction of 23.5% for the same specifications. The differential output stage proposed is able to generate pulses with a slew rate of 2V/ns, a frequency of 5MHz and voltage levels of 60, 80, 100 V using 0.039 mm2 of chip area. The power consumption is 0.951mW for a 30pF CMUT load. The design presented is implemented in a 0.35μm high-voltage process.

Synthesis and design of a fully integrated multi-topology switched capacitor DC-DC converter with gearbox control

This paper discusses a methodology of minimizing the amount of switches in a multi-topology fully integrated switched capacitor dc-dc converter powered by a super capacitor for energy harvesting purposes. The design of a simple controlling circuit for the multi-topology power stage using a gearbox approach is presented with all the required circuits. The converter is able to generate a output voltage of 1.2 V from a 470 mF capacitor charged to 3 V down to 1.4 V. The output voltage is regulated with a ripple voltage below 7 mV. The controlling circuit including buffers with ideal comparators has a power consumption of 129 μW, the average efficiency is 67% and the peak efficiency of the converter is 81%.

Switched capacitor DC-DC converter with switch conductance modulation and Pesudo-fixed frequency control

A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller is implemented in 180 CMOS with a 1/3 series-parallel output stage designed for 3.6–4.2 V input, 1.2 V output, and 1–40 mA load current. The proposed controller is compared with a co-integrated pulse skipping controller and yields a 84.8% reduction in worst-case low-load output ripple voltage and a 1.5% increase in peak efficiency reaching 92.5%, while also providing a predictable spectrum of the switching noise, reducing the risk of interfering with other sensitive circuits.

Area-efficiency trade-offs in integrated switched-capacitor DC-DC converters

This paper analyzes the relationship between efficiency and chip area in a fully integrated switched capacitor voltage divider dc-dc converter implemented in 180nm-technology and a 1/2 topology. A numerical algorithm for choosing the optimal sizes of individual components, in terms of power loss, based on the total chip area is developed. This algorithm also determines the optimal number of parallel phases in the converter, based on an estimate of power consumption in flip-flop based clock circuits. By these means the maximum achievable efficiency as a function of chip area is estimated.