Ivan Harald Holger Jørgensen

System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

In this paper a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front-ends and beamformation modules. The study focuses on the investigation of the effects of architectural design choices on the image quality. The point spread function is simulated in Field II from 10 to 160mm using a convex array transducer. A noise analysis is performed, and the minimum signal-to-noise ratio (SNR) requirements are derived for the low-noise amplifiers (LNAs) and A/D converters (ADCs) to fulfil the design specifications of a dynamic range of 60 dB and a penetration depth of 160mm in the B-mode image. Six front-end implementations are compared using Nyquist-rate and modulator ADCs. The image quality is evaluated as a function of the depth in terms of lateral full-width at half maximum (FWHM) and -12 dB cystic resolution (CR). The designs that minimally satisfy the specifications are based on a 8-bit 30MSPS Nyquist converter and a single-bit 3rd order 240 MSPS modulator, with a SNR for the LNA in both cases equal to 64 dB. The mean lateral FWHM and CR are 2.4% and 7.1% lower for the architecture compared to the Nyquistrate one. However, the results generally show minimal differences between equivalent architectures. Advantages and drawbacks are finally discussed for the two families of converters.

High-voltage pulse-triggered SR latch level-shifter design considerations

This paper compares pulse-triggered level shifters with a traditional level-triggered topology for high-voltage applications with supply voltages in the 50 V to 100 V range. It is found that the pulse-triggered SR (Set/Reset) latch level-shifter has a superior power consumption of 1800 μW/MHz translating a signal from 0-3.3 V to 87.5-100 V. The operation of this level-shifter is verified with measurements on a fabricated chip. The shortcomings of the implemented level-shifter in terms of power dissipation, transition delay, area, and startup behavior are then considered and an improved circuit is suggested which has been designed in three variants being able to translate the low-voltage 0-3.3 V signal to 45-50 V, 85-90 V, and 95-100 V respectively. The improved 95-100 V level shifter achieves a considerably lower power consumption of 438 μW/MHz along with a significantly lower transition delay. The 45-50 V version achieves 47.5 μW/MHz and a transition delay of only 2.03 ns resulting in an impressive FOM of 2.03ns/(0.35 μm 50 V) = 0.12ns/μmV.

Design and implementation of high frequency buck converter using multi-layer PCB inductor

Increasing the switching frequency for switch mode power supplies is one of methods to achieve smaller, lighter weight and cheaper power converters. This work investigates the opportunity of using two layer circular spiral inductors implemented in a 150 μm finished thickness printed circuit board for a high frequency DC-DC converter. The inductor was tested in a 5 W buck converter switching at 10 MHz. The converter achieved 84.7% peak efficiency converting 12 V to 5 V and 78% efficiency converting 24 V to 5 V.

Hardware-Efficient Implementation of Half-Band IIR Filter for Interpolation and Decimation

This brief deals with a simple heuristic method for the hardware optimization of a half-band infinite-impulse response (IIR) filter. The optimization method that is proposed here is intended for a quick design selection at the system level, without the need for computationally intensive calculations and simulations. The aim is to arrive at a design with low hardware complexity that is measured in terms of the number of adders. In the approach that is presented here, the filter specification is treated with some flexibility at the topmost system level. The half-band filter is implemented as a parallel connection of two all-pass filter cells. The filter is designed by first fixing the most sensitive filter coefficient to a convenient value that can be quantized by using only a few adders. Subsequently, the overdesign margin is used to coarsely quantize the remaining filter coefficients and thereby minimize hardware demands. The complexity of the resulting IIR filter is evaluated by counting all the adders in the filter, i.e., the adders for both the filter coefficients and the filter cells. The result of the method is compared with state-of-the-art works where the filter is designed by using the fixed filter specification and advanced algorithms to minimize the hardware that is used to implement filter coefficients.

A 10-bit 100 MSamples/s BiCMOS D/A Converter

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8µm BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5V, and has a power consumption of approximately 650mW. The area of the chip-core is 2.2mm × 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of fg≈0.1 fs(fs = 100MSamples/s) the measured SFDR is 50dB, and at fg≈0.3 fs the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase.

Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a new dual loop topology. The regulator utilizes the feedback loops to satisfy the challenges for hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0–100 pF capacitive load. The design has been implemented in a 0.18 μm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from 1.0 V–1.4 V supply. A current step load from 250–500 μA with an edge time (rise and fall time) of 1 ns results at ΔVOut of 64 mV with a settling time of 3 μs when CL =0. The power supply rejection ratio (PSRR) at 1 kHz is 63 dB.

Integrated differential high-voltage transmitting circuit for CMUTs

In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption at the scanner operation conditions is 0.754mW without the transducer load and 0.936mW with it.

Optimization and Design of a Low Power Switched Current A/D-ΣΔ-Modulator for Voice Band Applications

This paper presents a third order switched current ΣΔ-modulator. The modulator is optimized at the system level for minimum power consumption by careful design of the noise transfer function. A thorough noise analysis of the cascode type current copiers used to implement the modulator, together with a new methodology for evaluating the nonlinear settling behavior is presented. This leads to a new optimization methodology that minimize the power consumption in switched current circuits for given design parameters. The optimization methodology takes process variations into account. The modulator is implemented in a standard 2.4 μm CMOS process only using MOS capacitors. For a power supply of 3.3 V the power consumption is approximately 2.5 mW when operating at a sampling rate of 600 kHz. Under these condition the peak SNR it measured to 74.5 dB with a signal band width of 5.5 kHz. Due to internal clamping in the integrators and proper scaling the modulator shows excellent stability properties. In order to compare the performance of the modulator presented in this paper to other ΣΔ-modulators two figure-of-merits (FOMs) are proposed. From these figure-of-merits it is found that the performance of the modulator presented in this paper is significantely higher than the perforamce of other switched current ΣΔ-modulators reported. Also, the figure-of-merits show that the performance is comparable to the performance of reported switched capacitor ΣΔ-modulators.

System-Level Power Optimization of Digital Audio Back End for Hearing Aids

This work deals with power optimization of the audio processing back end for hearing aids—the interpolation filter, the sigma-delta (