Erik Bruun

A Chip for an Implantable Neural Stimulator

This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation (FES). The purpose of FES is to restore muscular control in disabled patients. The chip performs all the signal processing required in an implanted neural stimulator. The power and digital data transmission to the stimulator passes through a 5 MHz inductive link. From the signals transmitted to the stimulator, the chip is able to generate charge-balanced current pulses with a controllable length up to 256 μs and an amplitude up to 2 mA, for stimulation of nerve fibers. The quiescent current consumption of the chip is approx. 650 μA at supply voltages of 6–12 V, and its size is 3.9×3.5 mm2. It has 4 output channels for use in a multipolar cuff electrode.

CMOS high speed, high precision current conveyor and current feedback amplifier structures

Abstract Most current mode circuits presented so far have been realized in bipolar technology. The most prominent family of bipolar current mode circuits is the current feedback operational amplifier which is now available as a standard device from many of the semiconductor manufacturers specializing in analogue circuits. However, when integrating VLSI systems CMOS is normally the preferred technology and hence CMOS implementations of analogue functions, including current mode functions, is attracting widespread interest. In the present paper we examine CMOS versions of some fundamental current mode analogue circuit blocks (current conveyors) and show how each of the basic blocks have significant drawbacks, especially with respect to precision, compared to their bipolar counterparts. It is further shown how a combination of a few basic building blocks can yield current mode functions (conveyors and current feedback amplifiers) with a significantly improved performance. Experimental results from an integra...

Feedback analysis of transimpedance operational amplifier circuits

The transimpedance or current feedback operational amplifier (CFB op-amp) is reviewed and compared to a conventional voltage mode op-amp using an analysis emphasizing the basic feedback characteristics of the circuit. With this approach the paradox of the constant bandwidth obtained from CFB op-amps is explained. It is demonstrated in a simple manner that the constant gain-bandwidth product of the conventional op-amp and the constant bandwidth of the CFB op-amp are both in accordance with basic feedback theory and that the differences between the traditional op-amp and the CFB op-amp are due to different ways of controlling the closed-loop gain. For the traditional op-amp the closed-loop gain is altered by altering the loop gain, whereas the closed-loop gain in a CFB op-amp configuration is altered by altering the input attenuation to the feedback loop while maintaining a constant-loop gain. >

Dynamic range of low-voltage cascode current mirrors

Low-voltage cascode current mirrors are reviewed with respect to the design limitations imposed if all transistors in the mirror are required to operate in the saturation region. It is found that both a lower limit and an upper limit exist for the cascode transistor bias voltage. Further, the use of a signal dependent cascode bias voltage is discussed and a self-biased cascode configuration is presented. This configuration makes it possible to use a higher effective gate-source voltage for the mirror transistors, hence reducing the effect of threshold voltage mismatch on the current mirror gain. The proposed configuration has the advantage of simplicity combined with a complete elimination of the need for fixed bias voltages or bias currents in the current mirror. A disadvantage is that it requires a higher input voltage to the current mirror.

Bandwidth optimization of a low power, high speed CMOS current op amp

A current op amp with a differential output and a single-ended input can be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this design combines a high bandwidth with a high open loop gain. In this paper we present the basic configuration, derive the fundamental equations for the performance of the op amp, and describe some design considerations with respect to an optimization of the op amp for a high bandwidth. Simulation results are given from a commercially available 2µm CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128M H z at a supply voltage of 3V and a supply current of 25µA. The design has been experimentally verified through a test circuit and experimental results from this confirm the expected behaviour.

An implantable mixed analog/digital neural stimulator circuit

This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation. The chip performs all the signal processing required in an implanted neural stimulator. The power and signal transmission to the stimulator is carried out via an inductive link. From the signals transmitted to the stimulator, the chip is able to generate charge-balanced current pulses with a controllable length and amplitude for stimulation of nerve fibres. The chip has 4 output channels so that it can be employed in a cuff electrode with multiple connections to a nerve. The purpose of the functional electrical stimulation is to restore various bodily functions (e.g. motor functions) in patients who have lost them due to injury or disease.

A high-speed CMOS current op amp for very low supply voltage operation

A CMOS implementation of a high-gain current mode operational amplifier (op amp) with a single-ended input and a differential output is described. This configuration is the current mode counterpart of the traditional voltage mode op amp. In order to exploit the inherent potential for high speed, low voltage operation normally associated with current mode analog signal processing, the op amp has been designed to operate off a supply voltage of 1.5 V, and the signal path has been confined to N-channel transistors. With this design, a gain of 94 dB and a gain-bandwidth product of 65 MHz has been achieved at a power consumption of 30 /spl mu/W.<<ETX>>

Analysis of the Noise Characteristics of CMOS Current Conveyors

The definition of the current conveyor is reviewed and a multiple-output second generation current conveyor (CCII) is shown to combine the different generations of current conveyors presently existing. Next, noise sources are introduced, and a general noise model for the current conveyor is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches to an optimization of the noise performance are discussed. It is concluded that a class AB implementation can yield a lower noise output for the same dynamic range than a class A implementation. For both the class A implementation and the class AB implementation it is essential to design low noise current mirrors and current sources, and with the class AB design, the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current.

A differential-input, differential-output current mode operational amplifier

Abstract A current operational amplifier with differential input and differential output is described. The amplifier is based on the parallel connection of a CCII+ current conveyor and a CCII− current conveyor followed by a differential output transconductance gain stage. The performance of the amplifier is analysed and experimental results obtained from an implementation using standard operational amplifiers and current mirrors realized using transistor arrays are presented and compared to the theoretical analysis. It is concluded that the static small signal open loop gain and the frequency response matches the performance of conventional voltage operational amplifiers. The input offset and bias errors and the common mode rejection are shown to be strongly dependent on the matching accuracy of the current mirrors used in the conveyors. The proposed configuration can easily be integrated into a monolithic amplifier in either CMOS or bipolar technology.

Mixed analog/digital matrix-vector multiplier for neural network synapses

In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog twos complements method and an accurate current rectifier/sign detector. Measurements on a CMOS test chip are presented and validates the techniques. Further, we propose to use an analog extension, based on a simple capacitive storage, for enhancing weight resolution during learning. It is shown that the implementation of Hebbian learning and back-propagation learning in this system is possible using very little additional hardware compared to the recall mode system.