Dennis R. Conti

Mission impossible? Open architecture ATE

Summary form only given. A premise behind the open architecture system is to have a single set of hardware and software standards across the test industry, allowing instrumentation to be exchanged between ATE supplier boundaries. This paper asks whether the ATE suppliers will cooperate to set and maintain these standards while maintaining competition, and if not, looks at whether there is a sufficient number of third party suppliers to support multiple open architectures.

Wafer level burn-in

Is it the industrys intent to apply wafer-level burn-in (WLBI) to MPUs and ASICs? Package-level burn-in (PLBI) today is facing escalating burn-in power dissipation for these MPU and ASIC devices. The burn-in board (BIB) density (devices/BIB) varies inversely with device power dissipation. However, wafer-level burn-in would indicate the opposite-more devices in a 200 mm diameter. Is it the industrys intent to apply wafer-level burn-in to memory and more specifically, to DRAM? Here, the power situation is much less problematic than MPUs and ASICs. Yet, unlike logic DRAMs are overwhelmingly wirebonded die which require a test interface (probe) that can penetrate the bond pads aluminum oxide without damaging the wafer. There are multi-device under test (DUT) probe technologies available today for /spl times/32 DUT testing; they can cover an area of four square inches. And it may be possible to leverage these technologies to provide full wafer contact-but not for free. How would these compare to the PLBI economic model that we know and love? In the 1993-94 timeframe, several technology issues concerning WLBI were considered risky and required years to solve. So where is the design point today? Is WLBI a static burn-in methodology where applying elevated voltage and temperature is sufficient? Is it dynamic burn-in? Monitored burn-in? In situ burn-in? Or, will it naturally progress to wafer-level test and burn-in (WLTB)? This paper provides an overview of wafer-level burn-in, past and present, and offers a prediction for the future.

Testing the IBM Power 7™ 4 GHz eight core microprocessor

The IBM Power 7™ 4 GHz, eight core microprocessor introduced several new challenges for the Power 7 test team: new pervasive test architecture, 8 asynchronous processor cores, DRAM integrated on the same die as processor and enhanced thermal test requirements. The design complexity, time to market schedule compression, and rapid production ramp required innovation and new methods to meet these challenges. The following is an overview of the design for test architecture, manufacturing test methodology, thermal calibration, and rapid yield learning deployed to address these challenges and deliver a leadership server processor.