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Dive into the research topics where Deok-Soo Kim is active.

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Featured researches published by Deok-Soo Kim.


Nano Letters | 2009

Real-Space Mapping of the Strongly Coupled Plasmons of Nanoparticle Dimers

Deok-Soo Kim; Jinhwa Heo; Sung-Hyun Ahn; Sang Woo Han; Wan Soo Yun; Zee Hwan Kim

We carried out the near-field optical imaging of isolated and dimerized gold nanocubes to directly investigate the strong coupling between two adjacent nanoparticles. The high-resolution (approximately 10 nm) local field maps (intensities and phases) of self-assembled nanocube dimers reveal antisymmetric plasmon modes that are starkly different from a simple superposition of two monomeric dipole plasmons, which is fully reproduced by the electrodynamics simulations. The result decisively proves that, for the closely spaced pair of nanoparticles (interparticle distance/particle size approximately 0.04), the strong Coulombic attraction between the charges at the interparticle gap dominates over the intraparticle charge oscillations, resulting in a hybridized dimer plasmon mode that is qualitatively different from those expected from a simple dipole-dipole coupling model.


IEEE Journal of Solid-state Circuits | 2011

A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

Heesoo Song; Deok-Soo Kim; Dohwan Oh; Suhwan Kim; Deog-Kyoon Jeong

This paper describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) for multigigabit/s operation. The proposed digitally-controlled oscillator (DCO) incorporating a supply-controlled ring oscillator with a digitally-controlled resistor (DCR) generates wide-frequency-range multiphase clocks with fine resolution. With an adaptive proportional gain controller (APGC) which continuously adjusts a proportional gain, the proposed ADCDR recovers data with a low-jitter clock and tracks large input jitter rapidly, resulting in enhanced jitter performance. A digital frequency-acquisition loop with a proportional control greatly reduces acquisition time. Fabricated in a 0.13-μm CMOS process with a 1.2-V supply, the ADCDR occupies 0.074 mm2 and operates from 1.0 Gb/s to 4.0 Gb/s with a bit error rate of less than 10-14. At a 3.0-Gb/s 231 - 1 PRBS, the measured jitter in the recovered clock is 3.59 psrms and 29.4 pspp, and the power consumption is 11.4 mW.


Chemical Communications | 2008

Controlled synthesis and characterization of the enhanced local field of octahedral Au nanocrystals

Jinhwa Heo; Deok-Soo Kim; Zee Hwan Kim; Young Wook Lee; Dongheun Kim; Minjung Kim; Kihyun Kwon; Hyung Ju Park; Wan Soo Yun; Sang Woo Han

Octahedral Au nanocrystals with localized surface plasmon-assisted enhancing optical properties can be prepared in aqueous solution via the forced reduction of Au ions by ascorbic acid through the addition of NaOH.


asian solid state circuits conference | 2010

A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller

Deok-Soo Kim; Heesoo Song; Taeho Kim; Suhwan Kim; Deog-Kyoon Jeong

A 0.3-1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency detector (BBPFD), reducing output jitter. The fractional divider partially compensates for the large input phase error caused by fractional-N frequency synthesis. A fast frequency search unit using the false position method achieves frequency lock in 6 iterations that correspond to 192 reference clock cycles. A prototype ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC, a fractional divider, and a digital logic implementation of a frequency search algorithm was fabricated in a 0.13-μm CMOS logic process. The core occupies 0.2 mm2 and consumes 16.5 mW with a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak jitter with activating the ALGC are 3.7 ps and 32 ps respectively.


Optics Express | 2012

Role of in-plane polarizability of the tip in scattering near-field microscopy of a plasmonic nanoparticle

Deok-Soo Kim; Zee Hwan Kim

We report that a pyramid-shaped scanning probe microscopy tip has non-zero polarizability along the in-plane direction (perpendicular to the tip axis, z) at visible frequency. The in-plane polarizability enables the scattering-type scanning near-field optical microscopy (s-SNOM) to measure the in-plane field component around a plasmon-resonant nanoparticle. Because of the non-zero in-plane polarizability, the cross-polarized s-SNOM images may contain contributions from the in-plane field component of an out-of-plane plasmon mode as well as the out-of-plane field component of an in-plane mode. By comparing a scattering model and experimental s-SNOM images, we estimate the polarization anisotropies of pyramid-shaped Si-tips and metal-coated Si-tips.


international solid-state circuits conference | 2007

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

Dohwan Oh; Deok-Soo Kim; Suhwan Kim; Deog-Kyoon Jeong; Wonchan Kim

A 2.8Gb/s all-digital CDR uses a 10b glitch-free DCO which provides a 0.2 to 0.3% frequency tuning step to reduce the quantization effect. The CDR achieves 7.2psrms jitter at 2.5Gb/s and it operates from a 0.9 to 1.2V supply. The circuit occupies 300 times 430mum2 in a 0.13mum CMOS process and dissipates 13.2mW from a 1.2V supply when operating at 2.5Gb/s.


symposium on vlsi circuits | 2005

A spread spectrum clock generation PLL with dual-tone modulation profile

Deok-Soo Kim; Deog-Kyoon Jeong

This paper describes a spread spectrum clock generation (SSCG) PLL that uses a dual-tone modulation profile. The proposed modulation profile consists of the weighted sum of triangular waves. A mathematical analysis is applied to find out the optimum weight. Experimental results show that the /spl Delta/-/spl Sigma/ fractional-N PLL with the clock modulator exhibits better performance than a traditional SSCG by more than 2dB at the 630MHz operation.


ACS Nano | 2015

Stacking Structures of Few-Layer Graphene Revealed by Phase-Sensitive Infrared Nanoscopy

Deok-Soo Kim; Hyuksang Kwon; Alexey Yu. Nikitin; Seongjin Ahn; Luis Martín-Moreno; F. J. García-Vidal; S. Ryu; Hongki Min; Zee Hwan Kim

The stacking orders in few-layer graphene (FLG) strongly influences the electronic properties of the material. To explore the stacking-specific properties of FLG in detail, one needs powerful microscopy techniques that visualize stacking domains with sufficient spatial resolution. We demonstrate that infrared (IR) scattering scanning near-field optical microscopy (sSNOM) directly maps out the stacking domains of FLG with a nanometric resolution, based on the stacking-specific IR conductivities of FLG. The intensity and phase contrasts of sSNOM are compared with the sSNOM contrast model, which is based on the dipolar tip-sample coupling and the theoretical conductivity spectra of FLG, allowing a clear assignment of each FLG domain as Bernal, rhombohedral, or intermediate stacks for tri-, tetra-, and pentalayer graphene. The method offers 10-100 times better spatial resolution than the far-field Raman and infrared spectroscopic methods, yet it allows far more experimental flexibility than the scanning tunneling microscopy and electron microscopy.


international soc design conference | 2010

A 5.6 GHz LC digitally controlled oscillator with high frequency resolution using novel quadruple resolution varactor

Anil Kavala; Deok-Soo Kim; Sungchun Jang; Deog-Kyoon Jeong

This paper reports a high resolution LC-based digitally controlled oscillator (DCO) using novel quadruple resolution varactor. Proposed DCO has a high frequency resolution and a wide tuning range of 2.2 GHz with a low phase noise at 5.6 GHz. A process and temperature invariant quadruple resolution varactor is proposed to achieve the finest frequency resolution. The proposed varactor achieves one fourth capacitance of a fine varactor, and therefore DCO achieves a very fine frequency resolution with low phase noise. Also, the diode connected circuit makes the proposed varactor robust from the process and temperature variations. The DCO implemented in 0.13 μm CMOS process operates from 3.4 GHz to 5.6 GHz with a resolution from 260 Hz to 0.93 kHz by consuming a power from 5.5 mW to 3.2 mW, respectively. The designed DCO achieves a low phase-noise of −118 dBc/Hz at 1 MHz offset.


hawaii international conference on system sciences | 2016

A Stabilization Model for E-Government Innovation

Taehyon Choi; Deok-Soo Kim; Jungyun Ha

E-government innovations, which accompany both technological and administrative systems innovation, have often been driven more by technical fads than by social consensus. The structuration perspective on the adoption of technology has focused mainly on the organizational process, relatively ignoring the society-wide structuration that is more relevant to public organizations. In this paper, we focus on the structuration process of an e-government innovation, particularly the society-wide structuration through which enabled technical features are given meaning and legal institutionalization of use. Through the case, we found that an e-government system adopted for efficiency may suffer from the lack of an appropriate supporting legal structure, pushing the system into instability. We also found that the sophistication of an e-government system is based not only on its technological features but also on the evolution of social discourse. Finally, we discussed theoretical issues to further the knowledge of the structuration process of e-government innovations.

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Suhwan Kim

Seoul National University

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Byung Yang Lee

Seoul National University

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Heesoo Song

Seoul National University

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Seunghun Hong

Seoul National University

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Taekyeong Kim

Seoul National University

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Dohwan Oh

Seoul National University

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