Deog-Kyoon Jeong

An efficient charge recovery logic circuit

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-/spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-/spl mu/m CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm/sup 2/) and dissipates less power (42 mW) than other wide-range DLLs [2]-[7].

A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method

This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers infinite input impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18-/spl mu/m four-metal mixed-mode CMOS technology. The realized active area is 0.48/spl times/0.73 mm/sup 2/. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

A CMOS serial link for fully duplexed data communication

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 /spl mu/m CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns. >

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

This paper presents the design of a fully-integrated CMOS frequency synthesizer for PCS- and cellular-CDMA wireless systems. The proposed charge-averaging charge pump scheme suppresses fractional spurs and the VCO combined with coarse tuning improves phase noise characteristics. The improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. Fabricated in 0.35-/spl mu/m CMOS technology, this circuit provides 10 kHz channel spacing with phase noise of -106 dBc/Hz at 100 kHz offset. Power dissipation is 60 mW with 3.0 V supply.

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers and a DC-offset cancellation scheme. The direct conversion scheme combined with a multiphase sampling fractional-N prescaler alleviates the problems of the direct conversion transmitter and receiver. Digital gain control is merged into the baseband filters and variable-gain amplifiers to optimize the linearity of the system, reduce the noise, and improve the sensitivity. Variable-gain amplifiers with DC-offset cancellation loop eliminate the DC-offset in each stage. The chip implemented in 0.35-/spl mu/m CMOS technology shows the experimental results of 6 dBm maximum output power with 38-dB adjacent channel power rejection ratio at 1.92 MHz, 50-dB dynamic range, and 363-mW power consumption in the transmitter. The receiver shows -115.4 dBm sensitivity, a 4.0-dB noise figure, and a dynamic range of 80-dB with 396-mW power consumption.

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 /spl mu/m CMOS shows <10/sup -13/ BER for 2/sup 7/-1 PRBS (pseudo-random-bit-sequence) at 5GBaud.

A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS

A low-jitter 5000ppm spread-spectrum clock generator is implemented in a 0.18/spl mu/m CMOS process. By using 10 multi-phase clocks and a /spl Delta//spl Sigma/ modulator with periodic input, the chip has a deterministic jitter of 25ps due to spread-spectrum clocking and an amount of spreading of 5000ppm.

Multi-gigabit-rate clock and data recovery based on blind oversampling

This article addresses issues with designing a blind oversampling clock and data recovery unit (CDR) that meets jitter tolerance specifications. Asymptotic limits on jitter tolerance are derived assuming ideal phase detection based on a priori statistics of the received signal, proving that the coarse timing resolution of blind oversampling CDR relies on a phase detection algorithm that makes good estimates of the signals statistics with a finite number of discrete samples and at reasonable hardware costs. The statistical simulation methodology outlined here enables quick verification of the bit error rate and comparisons between the jitter tolerances of various blind oversampling CDR architectures.