Heesoo Song

A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

This paper describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) for multigigabit/s operation. The proposed digitally-controlled oscillator (DCO) incorporating a supply-controlled ring oscillator with a digitally-controlled resistor (DCR) generates wide-frequency-range multiphase clocks with fine resolution. With an adaptive proportional gain controller (APGC) which continuously adjusts a proportional gain, the proposed ADCDR recovers data with a low-jitter clock and tracks large input jitter rapidly, resulting in enhanced jitter performance. A digital frequency-acquisition loop with a proportional control greatly reduces acquisition time. Fabricated in a 0.13-μm CMOS process with a 1.2-V supply, the ADCDR occupies 0.074 mm2 and operates from 1.0 Gb/s to 4.0 Gb/s with a bit error rate of less than 10-14. At a 3.0-Gb/s 231 - 1 PRBS, the measured jitter in the recovered clock is 3.59 psrms and 29.4 pspp, and the power consumption is 11.4 mW.

A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller

A 0.3-1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency detector (BBPFD), reducing output jitter. The fractional divider partially compensates for the large input phase error caused by fractional-N frequency synthesis. A fast frequency search unit using the false position method achieves frequency lock in 6 iterations that correspond to 192 reference clock cycles. A prototype ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC, a fractional divider, and a digital logic implementation of a frequency search algorithm was fabricated in a 0.13-μm CMOS logic process. The core occupies 0.2 mm2 and consumes 16.5 mW with a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak jitter with activating the ALGC are 3.7 ps and 32 ps respectively.

43.3: Distinguished Paper: An Advanced Intra‐Panel Interface (AiPi) with Clock Embedded Multi‐Level Point‐to‐Point Differential Signaling for Large‐Sized TFT‐LCD Applications

In this paper, we present the newly developed intra-panel interface targeting to replace conventional multi-drop bus architecture with point-to-point differential interface. The multi-level signaling scheme is adopted to remove separate clock and control signal lines by embedding clock information into multi-level signal. The clock embedding scheme removes the skew problem found in previously announced intra-panel interface, and provides lower EMI. The simple multi-level signal detector is used to regenerate the clock signal from the data stream and does not require any sophisticated clock recovery unit in the receiver. The AiPi can be an effective solution to large size TFT LCD applications due to the reduced signal lines, lower EMI, and lower power consumption.

A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-㎛ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 ㎃ for a 400-㎷ output voltage swing.

A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter

This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental prototype was implemented in a 0.18 mum standard CMOS technology. A receiver that incorporates our CDR circuit has an active area of 380 mum times 350 mum.

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit

As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since the conventional intra-panel interfaces with multi-drop configurations, such as RSDS and mini-LVDS, increase the cost of overall systems at high bandwidth, new intrapanel interfaces have been proposed to meet the bandwidth requirement with point-to-point configurations [1–5]. This paper presents a new high-speed video interface that offers significant complexity reduction in the receiver. It is because receivers are integrated in a DDI with relatively slow high-voltage processes, while transmitters in host controllers are implemented with the more advanced deep-submicron processes. Compared to the PLL-based clock recovery circuits in [1–2], the DLL-based data recovery circuit occupies a smaller area with lower power consumption and offers unconditionally stable characteristics along with higher jitter tolerance.

A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines

We propose a high-resolution 8-bit time-to-digital converter that uses two-level fractional difference conversion to reduce area and power consumption. Two delay-locked loops stabilize the propagation delay in the upper and lower buffer chains of the Vernier delay line that is used to make the measurement. In a transistor-level simulation using 0.35um technology, this architecture achieves a resolution of 24ps with a 22ps single-shot accuracy. The maximum sampling rate exceeds 5MS/s and the total power consumption is 8.81mW.

A 1.3–330-MHz direct clock synthesizer for display interface using fractional multimodulus frequency divider

A 1.3-MHz to 330-MHz video clock synthesizer consisting of a fine-resolution fractional frequency divider and a divider-merged delta-sigma modulator (DSM) is presented. The proposed architecture provides a wide frequency range of output clock, and good jitter performance with reduced design complexity. Moreover, the divider-merged DSM guarantees the cycle-accurate frequency synthesis. The proposed fractional divider can divide the clock frequency with 4-bit fractional resolution using the proposed phase-switching technique. Fabricated in a 0.13-μm CMOS technology, the synthesizer has maximum peak-to-peak period jitter of 120 ps.

A 1.35GHz all-digital fractional-N PLL with adaptive loop gain controller and fractional divider

A 1.35GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang-bang phase-frequency detector (BBPFD). The fractional divider partially compensates for the input phase error which is caused by the fractional-N frequency synthesis operation. A prototype ADPLL using a BBPFD with a dead zone free retimer, an ALGC, and a fractional divider is fabricated in 0.13μm CMOS. The core occupies 0.19mm2 and consumes 13.7mW from a 1.2V supply. The measured RMS jitter was 4.17ps at a 1.35GHz clock output.