Deping Huang

A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver

This paper presents a wide-band fractional-N frequency synthesizer for multi-standard cellular and short-range wireless communication receivers. The synthesizer covers the frequency band from 1.8 to 6 GHz and supports the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802.11 a/b/g and Bluetooth. Architecture design and frequency planning are carefully performed to tradeoff wide frequency range and power efficiency. A quadrature voltage-controlled oscillator (QVCO) with a new phase shifter scheme is developed which shows better phase noise performance and more stable oscillation. Combining harmonic rejection and single sideband mixing, a harmonic-rejection SSBmixer (HR-SSBmixer) is developed to suppress unwanted sidebands and spurious signals. It serves as a power-saving solution to generate the LO signal for the 802.11a mode by avoiding power-hungry poly-phase filters or high-frequency LO buffers and dividers. The synthesizer is designed in a 0.13-μm CMOS technology. It occupies an active area of 1.86 mm2 and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer is able to provide in-phase and quadrature-phase (I/Q) signals supporting the standards mentioned above.

A 0.4–6-GHz Frequency Synthesizer Using Dual-Mode VCO for Software-Defined Radio

This paper presents a dual-mode voltage-controlled oscillator (DMVCO) and a DMVCO-based wideband frequency synthesizer for software-defined radio applications. The DMVCO allows the synthesizer to leverage single-sideband (SSB) mixing, a power efficient approach, for high-frequency local oscillator (LO) signal generation, without the need of poly-phase filter or quadrature voltage-controlled oscillator (QVCO). When compared to the QVCO approach, the DMVCO solution allows the synthesizer to provide continuous LO signals without frequency gaps. The synthesizer is implemented in a 0.13-μm CMOS technology, occupying an active area of 2.2 mm2 and consuming 34-77 mW of power. It provides in-phase and quadrature-phase LO signals over the frequency bands of 0.4-3- and 5-6 GHz and differential LO signals from 0.4 to 6 GHz, supporting major wireless standards including DVB-T, GSM, WCDMA, TD-SCDMA, WLAN802.11 a/b/g, and Bluetooth. The measured phase noises are -135 and -124 dBc/Hz at 3-MHz offset under 1.8- and 5.15-GHz carriers, respectively. The measured spurious tones are less than - 42 dBc at the SSB mixer output.

The miniature optical transmitter and transceiver for the High-Luminosity LHC (HL-LHC) experiments

We present the design and test results of the Miniature optical Transmitter (MTx) and Transceiver (MTRx) for the high luminosity LHC (HL-LHC) experiments. MTx and MTRx are Transmitter Optical Subassembly (TOSA) and Receiver Optical Subassembly (ROSA) based. There are two major developments: the Vertical Cavity Surface Emitting Laser (VCSEL) driver ASIC LOCld and the mechanical latch that provides the connection to fibers. In this paper, we concentrate on the justification of this work, the design of the latch and the test results of these two modules with a Commercial Off-The-Shelf (COTS) VCSEL driver.

A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13µm CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is −123dBc/Hz at 1MHz offset from a 1.8GHz carrier. The spectral purity is better than 45dBc from the output of mixer. The locking time of PLL is about 40µs with an AFC time less than 10µs. The 0.4–6GHz synthesizer consumes only 35mW to 51mW from a 1.2V supply.

The VCSEL-based array optical transmitter (ATx) development towards 120-Gbps link for collider detector: development update

A compact radiation-tolerant array optical transmitter module (ATx) is developed to provide data transmission up to 10Gbps per channel with 12 parallel channels for collider detector applications. The ATx integrates a Vertical Cavity Surface-Emitting Laser (VCSEL) array and driver circuitry for electrical to optical conversion, an edge warp substrate for the electrical interface and a micro-lens array for the optical interface. This paper reports the continuing development of the ATx custom package. A simple, high-accuracy and reliable active-alignment method for the optical coupling is introduced. The radiation-resistance of the optoelectronic components is evaluated and the inclusion of a custom-designed array driver is discussed.

A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver

This paper presents a Sigma-Delta fractional-N frequency synthesizer for multi-standard receiver. The synthesizers output range is 1.8~5.8GHz and covers the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802. Ha/b/g and Bluetooth. Frequency planning is elaborately done to make sure the synthesizer meets specifications of standards mentioned above. QVCO with a proposed phase shifter is shown to have better phase noise performance and more stable oscillation. Simulated phase noise is −119dBc/Hz at 1-MHz offset from a 4.2GHz carrier. Its FOM ranges from 181 to 187. The frequency synthesizer is fabricated in TSMC 0.13um CMOS process. Average power consumption is 55.92mW.

SET Detection and Compensation and Its Application in PLL Design

This paper presents a new charge compensation (CC) scheme to mitigate single event transient (SET) effect at the output node of the charge pump (CP), the most SET vulnerable node in a Phase-Locked Loop (PLL). It achieves a 4X less SET-induced voltage disturbance at the ring oscillator control node as well as a faster PLL recovery time. During the normal operation, the CC circuit does not affect the PLL dynamics. Its control block ensures that the CC circuit is enabled only when the CP output voltage is disturbed by SET strikes. This avoids the conflict between SET charge compensation and normal PLL phase correction. The PLL covers a 12.5 MHz to 500 MHz tuning range with a root-mean-square (RMS) jitter of 4.9 ps. It consumes 21.5 mW of power under a 1.5 V power supply. The CC circuit consumes 4.5 mW power and occupies 5.3% of the PLL area.

The clock distribution system for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade Demonstrator

A prototype Liquid-argon Trigger Digitizer Board (LTDB), called the LTDB Demonstrator, has been developed to demonstrate the functions of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. Forty Analog-to-Digital converters and four FPGAs with embedded multi-gigabit-transceivers on each Demonstrator need high quality clocks. A clock distribution system based on commercial components has been developed for the Demonstrator. The design of the clock distribution system is presented. The performance of the clock distribution system has been evaluated. The components used in the clock distribution system have been qualified to meet radiation tolerance requirements of the Demonstrator.

JTAG-based remote configuration of FPGAs over optical fibers

In this paper, a remote FPGA-configuration method based on JTAG extension over optical fibers is presented. The method takes advantage of commercial components and ready-to-use software such as iMPACT and does not require any hardware or software development. The method combines the advantages of the slow remote JTAG configuration and the fast local flash memory configuration. The method has been verified successfully and used in the Demonstrator of Liquid-Argon Trigger Digitization Board (LTDB) for the ATLAS liquid argon calorimeter Phase-I trigger upgrade. All components on the FPGA side are verified to meet the radiation tolerance requirements.

Implementation of direct frequency synthesizer for multiple frequency clock generation

This paper presents a low-jitter and high output frequency resolution direct frequency synthesizer (DFS) with phase interpolator (PI) based fractional divider (PIFD) for multiple frequency clock generation. Compared to conventional DFS, the proposed architecture offers higher frequency resolution, higher maximum frequency, better phase noise and jitter performance, as well as higher switching speed. In this paper, the fundamental jitter limitation of the synthesizer, due to the PI non-linearity and device mismatch, is analyzed in detail. It is shown that the PI non-linearity increases exponentially with the input signal intersection angle. In addition, the jitter from VCO is also taken into account. Designed and simulated in a 65nm CMOS technology, the frequency synthesizer provides a wide frequency range from 8MHz to 8GHz, with frequency resolution 8MHz. The maximum switching time is limited by the output clock period. The best RMS jitter is 3ps @ 8GHz when NpI=0 and the worst-case RMS jitter is 12ps @ 7.994GHz when NpI=35. The spurious free dynamic range is 56dBc in worst case.