Chonghan Liu

The design of 8-Gbps VCSEL drivers for ATLAS liquid Argon calorimeter upgrade

We present designs and preliminary test results of LOCld1 and LOCld4, VCSEL drivers in a commercial 0.25-mu m m Silicon-on-Sapphire (SoS) CMOS process for ATLAS liquid Argon calorimeter upgrade. Active shunt peaking, multiple-stage amplification and higher voltage supply are used to achieve the data rate of 8 Gbps. LOCld1 is a single channel VCSEL driver with a differential output, while LOCld4 has four channels with single-ended open-drain outputs. Both drivers have tunable modulation and peaking strength. Bias current for VCSEL is also embedded.

The miniature optical transmitter and transceiver for the High-Luminosity LHC (HL-LHC) experiments

We present the design and test results of the Miniature optical Transmitter (MTx) and Transceiver (MTRx) for the high luminosity LHC (HL-LHC) experiments. MTx and MTRx are Transmitter Optical Subassembly (TOSA) and Receiver Optical Subassembly (ROSA) based. There are two major developments: the Vertical Cavity Surface Emitting Laser (VCSEL) driver ASIC LOCld and the mechanical latch that provides the connection to fibers. In this paper, we concentrate on the justification of this work, the design of the latch and the test results of these two modules with a Commercial Off-The-Shelf (COTS) VCSEL driver.

LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade

In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-μm Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.

8-Gbps-per-channel radiation-tolerant VCSEL drivers for the LHC detector upgrade

We present ASIC designs of VCSEL drivers for a single VCSEL (LOCld1), two individual VCSELs (LOCld2) and a four-channel VCSEL array (LOCld4). This work is for new detector readout systems needed in the Large Hadron Collider upgrade program. All ASICs are fabricated in a commercial 0.25-μ m Silicon-on-Sapphire CMOS technology. LOCld1 and LOCld2 have passed the 8-Gbps and 10-Gbps eye mask tests. Operating at 8 Gbps data rate, the measured total jitter of LOCld1 and LOCld2 is less than 30 ps, and the power comsuption is about 200 mW per channel with 6-mA bias current and 6.4-mA modulation current. The radiation tolerance of LOCld1 has been qualified with x-ray and high-energy neutron beam test.

Response of a 0.25 μm thin-film silicon-on-sapphire CMOS technology to total ionizing dose

The radiation response of a 0.25 μm silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. The threshold-voltage shift is less than 170 mV and the leakage-current increase is less than 1 nA for individual standard-layout nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power supply current at the circuit level was less than 5%, consistent with the small change in off-state transistor leakage current. The technology exhibits good characteristics for use in the electronics of the ATLAS experiment at the Large Hadron Collider.

A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments

We propose a line code that has fast resynchronization capability and low latency. Both the encoder and decoder have been implemented in FPGAs. The encoder has also been implemented in an ASIC. The latency of the whole optical link (not including the optical fiber) is estimated to be less than 73.9 ns. In the case of radiation-induced link synchronization loss, the decoder can recover the synchronization in 25 ns. The line code will be used in the ATLAS liquid argon calorimeter Phase-I trigger upgrade and can also be potentially used in other LHC experiments.

Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments.

Design and verification of a bit error rate tester in Altera FPGA for optical link developments

This paper presents a custom bit error rate (BER) tester implementation in an Altera Stratix II GX signal integrity development kit. This BER tester deploys a parallel to serial pseudo random bit sequence (PRBS) generator, a bit and link status error detector and an error logging FIFO. The auto-correlation pattern enables receiver synchronization without specifying protocol at the physical layer. The error logging FIFO records both bit error data and link operation events. The testers BER and data acquisition functions are utilized in a proton test of a 5 Gbps serializer. Experimental and data analysis results are discussed.

The clock and control system for the ATLAS Liquid Argon Calorimeter Phase-I upgrade

A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to upgrade the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system is being developed for the LTDB and the major functions of the system have been evaluated. The design and evaluation of the clock and control system are presented in this paper.

The VCSEL-based array optical transmitter (ATx) development towards 120-Gbps link for collider detector: development update

A compact radiation-tolerant array optical transmitter module (ATx) is developed to provide data transmission up to 10Gbps per channel with 12 parallel channels for collider detector applications. The ATx integrates a Vertical Cavity Surface-Emitting Laser (VCSEL) array and driver circuitry for electrical to optical conversion, an edge warp substrate for the electrical interface and a micro-lens array for the optical interface. This paper reports the continuing development of the ATx custom package. A simple, high-accuracy and reliable active-alignment method for the optical coupling is introduced. The radiation-resistance of the optoelectronic components is evaluated and the inclusion of a custom-designed array driver is discussed.