Derryl Allman

Impact of via interactions and metal slotting on stress induced voiding

Stress induced voiding was investigated for a 0.13 mum Cu/low-k interconnect process. The focus of our study was on the ldquohumprdquo failure mode using a statistical approach to both the design of the vehicle and the data analysis. The time-to-failure (TTF) was studied with respect to geometrical aspects of the lower metal level, insertion of a dummy via, via arrays and metal slotting for long via chains. It is found that insertion of dummy vias increased the reliability, through reduction in the probability for void nucleation and a reduction in void growth rate. The lifetime improvement is attributed to a stress modification in the interconnect. The stress modification can effect vias far from the local ldquodiffusive volumerdquo during void growth, indicating possible new approaches for redundant electrical or dummy via placement. Insertion of metal slots close to the electrically active via act as a diffusive barrier, and slots located elsewhere can modify the stress in the interconnect to improve via lifetime.

On the distribution of stress-induced voiding failures under vias

A physics-of-failure model is derived for the statistics of open-failure mode stress induced voiding (SIV) for vias contacting wide lower metal leads. This model is used to fit long-term, low-temperature data from a 130 nm Cu/low-k BEOL process. Scaling forms are discussed for the temperature acceleration, via chain length, and linewidth. A single void growth model can be used to fit the apparent separate Weibull modes in the data, and for very long chains a three-parameter Weibull is found as a limiting distribution. Monte Carlo integration over the via size is also used to verify the model. The presence of early transient statistics emphasize the practical importance of the sample size and stress testing readout strategy.

Reliability evaluations of ECP tools and chemistries

Microstructural considerations were studied in a tool qualification for ECP in a dual-damascene 110nm Cu/low-k BEOL process. Wafer Level tests (HTS, Isothermal EM) using standard SM/SIV and EM test structures were used to compare two ECP tools and chemistries, and sensitivities were further investigated with materials analysis consisting of Elemental (TOF-SIMS), EBSD (texture analysis) and grain-size analysis. It is found that the differences in the relative grain-size, and impurity content both contributed to the improvement of the TTF for EM and SM/SIV. Interpretation of the SIV data used a proportional hazards model, incorporating basic elements of stochastic geometry to find a scaling form which can be used to extract the relative change in Cu mobility.

An evaluation of accelerated failure time models of stress-migration and stress-induced voiding failures under vias

This paper extends a previously published model [1] of stress induced voiding (SIV) to the case where diffusion proceeds according to a power-law in the initial stress. The model is used to fit long-term, low-temperature (30°C) data from a 130 nm Cu/low-k BEOL process. In some cases, the data supports the use of a power-law void growth as evidenced by a “fattening” of the long-time tail in the failure statistics. The mechanisms for low-temperature power-law void-growth include: (1) dislocation creep from climbing dislocations within the Cu grains, (2) superposition of multiple stress-relaxation paths, and (3) statistical mixing of distributions. While statistical mixing is dealt with by stratifying the data by position on the wafer, it is not possible to separate the mechanisms of creep and multiple stress relaxation modes. The accurate assessment of the tail of the distribution is important for establishing the impact of scaling parameters on the reliability, in order to establish design-rules for zero failures due to SIV.

Plasma Enhanced Atomic Layer Deposition of Al 2 O 3 /SiO 2 MIM Capacitors

Metal-insulator-insulator-metal (MIIM) capacitors with bilayers of Al₂O₃ and SiO₂ are deposited at 200 °C via plasma enhanced atomic layer deposition. Employing the cancelling effect between the positive quadratic voltage coefficient of capacitance (αVCC) of Al₂O₃ and the negative αVCC of SiO₂, devices are made that simultaneously meet the International Technology Roadmap for Semiconductors 2020 projections for capacitance density, leakage current density, and voltage nonlinearity. Optimized bilayer Al₂O₃/SiO₂ MIIM capacitors exhibit a capacitance density of 10.1 fF/μm², a leakage current density of 6.8 nA/cm² at 1 V, and a minimized αVCC of -20 ppm/V².

Atomic layer deposition of bismuth oxide using Bi(OCMe2iPr)3 and H2O

This is the publisher’s final pdf. The article is copyrighted by the American Vacuum Society and published by the American Institute of Physics Publishing. It can be found at: http://scitation.aip.org/content/avs/journal/jvsta.

Investigation of growth parameter influence on hydrothermally grown ZnO nanowires using a research grade microwave

Hydrothermal growth methods allow for low-temperature synthesis of ZnO nanowires (NWs) directly on a variety of novel substrates required for proposed flexible substrate applications such as power-harvesting fabrics [1]. Although hydrothermal growth opens up a new realm of application possibilities, a major drawback of this method is growth time — up to 20 hours or longer have been reported as necessary to yield desired NW morphologies [2]. The use of microwave heating of the nutrient solution has recently been reported to speed the growth process [3]. Although hydrothermal growth temperature has been reported to be a critical process variable [4], the conventional microwave used previously [3] did not offer a direct method of controlling process temperature. Instead, indirect control of growth temperature was attempted by microwave power level adjustment. Other typical microwaves change power level through variations in duty cycle. In this work, a research grade microwave oven, equipped with integrated temperature control, was used to systematically investigate the impact of growth temperature, growth time, and solution concentration on ZnO NW length, diameter, aspect ratio, growth orientation, density, and wire morphology.

Hydrothermal Synthesis of Zinc Oxide Nanowires on Kevlar using ALD and Sputtered ZnO Seed Layers

Low temperature hydrothermal methods allow for growth of nanowires on novel substrates. We examine the impact of variations in chemical concentration, time, temperature, and seed layer on nanowire (NW) growth and crystallite formation. The majority of growth (NWs and crystallites) was found to occur within the first two hours. Lower Zn(NO3)2 concentrations produced a reduction in the undesired large crystallites, whereas hexamethylene tetramine (HMT) concentration did not largely impact crystallite density or nanowire morphology. Growth temperature appeared to impact NW diameter variation. Nanowires grow only on the ZnO seed layer and crystallites seem to attach preferentially to the bare Kevlar surface.

Engineering the failure-free lifetime for Cu vias

Stress induced void (SIV) nucleation and growth is studied using phenomenological creep models and used to predict failure rates in Cu/low-k via chains from a 110nm process. It is argued that the void formation is induced at grain-boundaries, triple-junctions, and microstructural changes due to the local stress concentrations and stress-gradients inducing micro-fracture and subsequent flux divergence. The longer term stress-relaxation is described by a power-law in the thermal stress. Experiments are performed to verify the impact of via adhesion, via gouging, via diameter, via placement in extensions relative to large metal leads, and geometrical variations in the metal layer. High Temperature Storage (HTS) tests completed at 125 to 250° are compared to long-term, low-temperature (30° C) data to verify the acceleration model. Our data indicates that a failure-free lifetime (FFL) may exist for certain geometries, and new scaling relationships are used to establish conditions where SIV does not impact the long-term reliability of Cu vias. A novel HTS protocol is suggested for scaling to immortal vias using the right hand side of the cumulative distribution function and model fitting to a generalized Pareto distribution, where the Pareto parameter is equal to the power-law of the stress-relaxation. The short-term and long-term HTS protocols are linked in the model, so that measurement of one can provide information about the other, allowing for the use of the distribution to establish process and design factors that ensure high reliability.

Interactions and self-healing of Cu vias during stress migration tests and implications for burn-in and design rule formulations

During High Temperature Storage (HTS), previously failed vias due to open failures from voids subsequently self-heal. Likewise, the resistance shifts appear to saturate and reverse direction over long times. The propensity for self-healing and subsequent “immortality” can be explained in a physical model by an interaction between voids and material sinks (such as grain boundaries) analogous to growing second-phases in late-stage precipitation — also called Ostwald ripening. HTS data is collected from a 130 nm Cu/low-k BEOL process, with various geometrical variations, single and multiple vias, initial resistances and processing. Resistance shifts and open failures are tracked and modeled. The model is based on formulating a mean-field, which is the volume averaged stress due to the arrays of voids and the material shed during their growth. This model takes into account the surface energy of the growing void through the sintering stress as a boundary condition. A key outcome of this formulation is a critical void radius in equilibrium with the mean stress, where, voids with a supercritical radius will grow at the expense of voids with subcritical radius. The maximum void size is modified by the surface energy and the elastic modulus. We show that the saturated void radius (SVR) is truly an upper bound on the size of any particular void. We demonstrate the implications for reliability and engineering design through scaling relationships well as indicate directions for further experimental and theoretical study.