Sallie Hose

New modular high voltage LDMOS technology based on Deep Trench Isolation and 0.18um CMOS platform

This paper presents the challenges of integrating 70V and 45V lateral DMOS transistor modules into a 0.18um base line process. This integration is achieved with minimal impact on baseline process and circuit IPs. Multi-epitaxial stack and Deep Trench Isolation (DTI) modules assure up to 140V isolation capability between different areas in the chip.

Plasma Enhanced Atomic Layer Deposition of Al 2 O 3 /SiO 2 MIM Capacitors

Metal-insulator-insulator-metal (MIIM) capacitors with bilayers of Al₂O₃ and SiO₂ are deposited at 200 °C via plasma enhanced atomic layer deposition. Employing the cancelling effect between the positive quadratic voltage coefficient of capacitance (αVCC) of Al₂O₃ and the negative αVCC of SiO₂, devices are made that simultaneously meet the International Technology Roadmap for Semiconductors 2020 projections for capacitance density, leakage current density, and voltage nonlinearity. Optimized bilayer Al₂O₃/SiO₂ MIIM capacitors exhibit a capacitance density of 10.1 fF/μm², a leakage current density of 6.8 nA/cm² at 1 V, and a minimized αVCC of -20 ppm/V².

Atomic layer deposition of bismuth oxide using Bi(OCMe2iPr)3 and H2O

This is the publisher’s final pdf. The article is copyrighted by the American Vacuum Society and published by the American Institute of Physics Publishing. It can be found at: http://scitation.aip.org/content/avs/journal/jvsta.

Gate oxide yield improvement for 0.18µm power semiconductor devices with deep trenches

Two unique gate oxide failure mechanisms are associated with deep trench processes for a 0.18 µm power semiconductor device. One failure mode is a “mini-LOCOS” defect, that is due to inadvertent oxidation of Si in the active area during deep trench oxidation. The other failure mode is due to slip associated with dislocations from the deep trenches. These defects are eliminated by optimizing the SiN oxidation barrier used during deep trench oxidation and by optimizing high temperature anneals to minimize dislocation generation.

Stability study of native epitaxial transistors as process probe for contamination detection

Methods for detecting contamination with native transistor probes are reviewed. This review is based on experience which was accumulated during development of multi-level epitaxial (EPI) high voltage DMOS process technologies including Deep Trench Isolation (DTI) with isolation capabilities up to and above 100V. Potential contamination sources, mechanisms and characterization are critically discussed. Authors identified five sources of dopant contamination: device EPI architecture, backside seal film budget, pre/post EPI cleans, cross tool contamination and high energy implants. Native NMOSFET device was used for detecting the low dopant contamination levels. Analyzing unique wafer patterns for native transistor threshold voltage can help point to a solution path.

Atomic layer deposition of bismuth oxide using Bi(OCMe{sub 2}{sup i}Pr){sub 3} and H{sub 2}O

This is the publisher’s final pdf. The article is copyrighted by the American Vacuum Society and published by the American Institute of Physics Publishing. It can be found at: http://scitation.aip.org/content/avs/journal/jvsta.

Atomic layer deposition of bismuth oxide using Bi(OCMe₂ [superscript i]Pr)₃ and H₂O

This is the publisher’s final pdf. The article is copyrighted by the American Vacuum Society and published by the American Institute of Physics Publishing. It can be found at: http://scitation.aip.org/content/avs/journal/jvsta.