Detlev Theil

A low-IF RX two-point /spl Sigma//spl Delta/-modulation TX CMOS single-chip Bluetooth solution

A new low-cost concept for a system-on-chip Bluetooth solution is proposed in this paper. The single chip includes all necessary baseband and RF parts to achieve full Bluetooth functionality and is implemented in a standard 0.25-/spl mu/m CMOS technology. The two-point modulation /spl Sigma//spl Delta/ fractional N phase-locked loop achieves a phase noise of -124 dBc/Hz at 3-MHz offset. The sensitivity of the embedded low-IF receiver is measured to be -82 dBm at a bit error rate of 0.1%. The power supply voltages for the digital and analog parts are internally regulated to 2.65 V. The maximum current consumption of the analog part is 60 mA.

A fully integrated CMOS frequency synthesizer for Bluetooth

A low power, fully integrated 2.4 GHz fractional-N frequency synthesizer for Bluetooth in a 0.25 /spl mu/m CMOS technology is presented. The complete synthesizer, including a fully integrated VCO, consumes 22 mA from a 2.5 V supply. The integrated VCO reaches a phase noise of -133 dBc/Hz at 3 MHz. The synthesizer is designed for a direct /spl Sigma//spl Delta/-modulation of the PLL.

CMOS Radio with an Integrated 26dBm Power Amplifier for a Complete System-on-Chip Cordless Phone

A fully integrated transceiver in a 0.13 mum CMOS technology including on-chip power amplifier (PA) for digital cordless telephone standards is presented. The PA exhibits an output power of POUT = 26 dBm. The implemented frequency synthesizer shows robustness against PA coupling, excellent phase noise performance and fast settling time. The fully integrated receiver deploys a low intermediate frequency (IF) architecture with a very low noise, low current consumption front-end and a complex band pass filter for channel selection. The receiver is measured to achieve a sensitivity level of P0.1% = -96 dBm. The transceiver uses ITX = 35 mA in transmit mode and IRX = 25 mA in receive mode from a regulated VTRX = 1.5 V supply. The PA shows a power added efficiency (PAE) of more than 30% at a VPA = 2.5 V direct-connect-to-battery supply. The transceiver is developed as a part of a complete system-on-chip (SoC) cordless phone.

Fully integrated CMOS GPS receiver for system-on-chip solutions

A CMOS receiver for the Global Positioning System (GPS) is presented. It is designed in a 0.13mum standard CMOS process and is fully integrated for the needs of a system-on-chip (SoC) solution for GPS and assisted GPS (A-GPS). It provides the needed frequency conversion, gain and filtering for GPS signals without any other external components than those required for matching and decoupling. The receiver includes the local oscillator (LO) signal generation and all needed supply voltage regulators. The achieved noise figure (NF) of the receiver is 1.8dB, including losses of external filtering for blocking requirements

A high performance CMOS LNA for system-on-chip GPS

A 1.6 GHz CMOS single-ended low noise amplifier (LNA) optimized for integration and use in Global Positioning System (GPS) applications is presented. The LNA is implemented in a 0.13 mum standard CMOS process with on-chip inductors. The LNA achieves a noise figure of 1.35 dB, a power gain of 16.7 dB and a 1 dB compression point of -14 dBm at a current consumption of 8.5 mA from a 1.8 V supply. The penalty of digital crosstalk on the noise figure is measured to 0.2 dB.