Stefan Heinen

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

A 2nd-order continuous-time quadrature bandpass /spl Sigma//spl Delta/ modulator with 1 MHz IF clocked at 100 MHz digitizes I and Q inputs with SNDR of 56.2 dB for 1 MHz bandwidth inputs. The 0.65 /spl mu/m BiCMOS chip consumes 21.8 mW at 2.7 V, and operates with a clock-frequency range of 25-100 MHz.

A low-IF RX two-point /spl Sigma//spl Delta/-modulation TX CMOS single-chip Bluetooth solution

A new low-cost concept for a system-on-chip Bluetooth solution is proposed in this paper. The single chip includes all necessary baseband and RF parts to achieve full Bluetooth functionality and is implemented in a standard 0.25-/spl mu/m CMOS technology. The two-point modulation /spl Sigma//spl Delta/ fractional N phase-locked loop achieves a phase noise of -124 dBc/Hz at 3-MHz offset. The sensitivity of the embedded low-IF receiver is measured to be -82 dBm at a bit error rate of 0.1%. The power supply voltages for the digital and analog parts are internally regulated to 2.65 V. The maximum current consumption of the analog part is 60 mA.

A fully integrated CMOS frequency synthesizer for Bluetooth

A low power, fully integrated 2.4 GHz fractional-N frequency synthesizer for Bluetooth in a 0.25 /spl mu/m CMOS technology is presented. The complete synthesizer, including a fully integrated VCO, consumes 22 mA from a 2.5 V supply. The integrated VCO reaches a phase noise of -133 dBc/Hz at 3 MHz. The synthesizer is designed for a direct /spl Sigma//spl Delta/-modulation of the PLL.

Functional Verification of Radio Frequency SoCs using Mixed-Mode and Mixed-Domain Simulations

The main focus of this work is the functional verification of radio frequency (RF) transceivers and RF systems on chip (SoCs). The use of enhanced baseband behavioral description models for an industrial available multiband, low IF GSM receiver is demonstrated. The necessity of functional verification when dealing with complex baseband signals and mixing operations with high/low sideband possibilities is shown. Future demands on language constructs and their implementations into the design flow are presented. Fundamental simulation comparisons for different implementation levels and proposals for new constructs to ensure functionality and connectivity between advanced behavioral description level and transistor schematics are made. This paper concludes with a suggestion for an extension of the Verilog-HDL-family to aid SoC designers in their effort to shorten the time to market and demonstrates the possible benefits of upcoming systemVerilog constructs

The first very low-IF RX, 2-point modulation TX CMOS system on chip Bluetooth solution

The proposed low cost Bluetooth single-chip solution is implemented in a 0.25 /spl mu/m CMOS technology. The System On Chip (SOC) includes all necessary baseband- and RF-parts to achieve full Bluetooth functionality, by occupying 18.5 mm/sup 2/ chip area in total. The maximum current consumption of the analog part is 60 mA. The internal regulated supply voltages of the analog and digital parts are 2.65 V. First measurement results of basic functionalities are discussed in this paper.

Using a dataflow abstracted virtual prototype for HdS-design

The complexity of Hardware-dependent Software (HdS) continuously grows faster than chip complexity since more and more tasks aremoved to software. Clearly, the pressure on the development of new methodologies for early validation of HdS increases as well. Existing methods must be continuously improved and new methods must be developed. This is exemplified with an state-of-the-art Transaction Level (TL) model used for firmware development of a productive wireless communication chip. By discussing the strengths and shortcomings of TL modeling we derive a set of requirements for a future modeling paradigm, which led to the new data flow abstraction approach presented in this paper. Experiments showed that we gain up to 10x performance improvement.

An RF transceiver for WDCT in a 25 GHz Si bipolar technology

An RF Si bipolar transceiver IC for WDCT is presented. The complete transceiver operates from 3.1 V to 5.1 V and provides very high integration level. The receiver uses a single conversion architecture with an image-reject frontend and needs no external trimming.A RF Si bipolar transceiver IC for WDCT is presented. The complete transceiver operates from 3.1 V to 5.1 V and provides very high integration level. The receiver uses a single-conversion architecture with an image-reject frontend and needs no external trimming.

A fully-integrated BiCMOS voltage-controlled oscillator for DECT application

A voltage-controlled oscillator (VCO) with an integrated inductor and varactor diodes achieves -139 dBc/Hz phase noise at 6.4 MHz frequency offset in the 1880-1900 MHz DECT band. The VCO has 250 MHz tuning range and 125 MHz/V gain which is enough to compensate production tolerances. The monolithic circuit is fabricated in a 0.5 /spl mu/m 25 GHz f/sub T/ BiCMOS process.

Joint source and channel coding: from the beginning until the ‘EXIT’

The speech quality in digital mobile communications is improved by using the residual redundancy after speech encoding in source decoding or channel decoding. The latter was investigated at the LNT at Munich University of Technology, the first idea at the IND at RWTH Aachen University. When the two institutes got aware of each others results, a friendly scientific competition was started by investigating ‘source-controlled channel decoding’ (SCCD) at the LNT and ‘source optimised channel codes’ (SOCC) at the IND. It turned out, a combination of the two separate approaches would be the best, which led to a fruitful cooperation. The outcome was the ‘joint source and channel coding’ approach, the iterative source and channel decoding (ISCD) and its improvement by applying the extrinsic information transfer (EXIT) chart analysis. In this paper we give a summary of the algorithms and their performances. We also take a look onto the application of the algorithms to real world systems. Copyright

The first near zero-IF RX, 2-point modulation TX CMOS SOC Bluetooth solution

The proposed new low cost concept for a CMOS System On Chip (SOC) Bluetooth Solution is called BlueMoonSingle. The BlueMoonSingle includes the baseband-part as well as the RF-part of a Bluetooth system. Aspects of the analog/digital RF-part of the BlueMoonSingle are introduced. The single-chip solution has been fabricated in a 4 metal 0.25 /spl mu/m CMOS technology and requires 18.5 mm/sup 2/ chip area in total. The internal regulated power supply voltages are 2.65 V, the maximum current consumption of the analog part is 60 mA. First measurement results of basic functionalities are discussed in this paper.