Devendra Kumar Sharma

VLSI interconnects and their testing: prospects and challenges ahead

Purpose – The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.Design/methodology/approach – In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requiremen...

Effect of Mutual Inductance and Coupling Capacitance on Propagation Delay and Peak Overshoot in Dynamically Switching Inputs

The shrinking feature size of MOSFET devices is largely responsible for growth of VLSI circuits. In DSM technology below 0.18 µm, interconnect parasitics are significant and erupt as performance limiting parameters of the circuit. Because of short spacing between interconnects, faster signal rise time, longer wire length and use of low K-dielectric material, the coupling capacitance (CC) and mutual inductance (M) are introduced among on-chip interconnects. This paper presents in-depth analysis of the effects of coupling parasitics on wire propagation delay and peak overshoot voltage for both in phase and opposite phase switching of inputs. To support our analysis, two distributed RLC interconnects coupled inductively and capacitively are taken into consideration. For capturing the effects of coupling parasitics, interconnects are simulated and SPICE waveforms are generated at far end of transmission line. It is illustrated that inductive and capacitive couplings have conflicting effects on wire propagation delay. However, the effect on peak overshoot voltage is of different kind.

Dynamic Crosstalk Analysis in RLC Modeled Interconnects Using FDTD Method

Accurate time domain analysis and cross talk estimation in VLSI interconnects has emerged as an essential design criteria. This paper presents the description of a finite difference time domain (FDTD) method that is intended for estimation of voltages and currents on coupled transmission line. A numerical method based on FDTD is opted for the estimation of cross talk induced time delay in lossy RLC interconnects. Both functional and dynamic cross talk effects in coupled line configuration are analyzed. Effect of line resistance on delay is also evaluated. A linear resistive driver is used to drive distributed RLC transmission line for lossy interconnect. It has been observed that the analytical results for proposed FDTD model are in good agreement with HSPICE simulation results. The proposed model using FDTD results in an average error of 4.1% with respect to HSPICE.

A Qualitative Approach to Optimize Coupling Capacitance for Simultaneously Switching Scenario in Coupled VLSI Interconnects

In DSM technology and beyond, the performance and correctness of the circuit cannot be assured without taking into consideration the multiple effects of interconnect parasitics. The inter wire parasitics i.e. mutual inductance and coupling capacitance are primary sources of crosstalk noise. In this paper, the optimization of coupling capacitance for delay and peak noise is carried out qualitatively. This optimization process is essential from the fact that propagation delay and peak noise in some cases show opposite behavior with change in coupling capacitance. For our study, two distributed RLC lines coupled inductively and capacitively are considered. A pair of interconnect lines each of 4mm length and terminated by capacitive load of 30 fF with varying capacitive and inductive couplings are simulated. The SPICE waveforms are generated for simultaneous switching of inputs at far end of lines. The simulation is carried out for 130nm, 1.5 V technology node. The width of driver PMOS and NMOS are taken as 70 µm and 35 µm respectively.

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line & coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.

Crosstalk effect in coupled interconnect lines using FDTD method

Technological advancement below 65nm has resulted in high speed complex VLSI interconnects. As an essential design criterion, these high frequency interconnects require accurate analysis in time/frequency domain and crosstalk estimation. This research work employs the finite difference time domain (FDTD) method for estimation of voltages and currents on coupled transmission line. Moreover, crosstalk delay in RLC interconnects is analyzed using FDTD method. Both functional and dynamic crosstalk effects in coupled line configuration are analyzed. Effect of line resistance on delay is also evaluated. A linear resistive driver is used to drive distributed RLC transmission line. Encouragingly, analytical results for proposed FDTD model are in good agreement with HSPICE circuit simulation results.

Effect of aggressor driver width on crosstalk for static and dynamic switching of victim line

In DSM technology, unintended interactions between signals propagating through interconnect turn out to be critical design concern. At technology nodes below 0.25μηι, the performance and correctness of a design cannot be assured without considering noise effects. In integrated circuits, the main cause of signal integrity problems is crosstalk. This paper presents the effects of aggressor driver width variation on crosstalk noise in RLC coupled interconnects for static and dynamic switching of victim line. To demonstrate these effects, two distributed RLC interconnects coupled inductively and capacitively are taken into consideration. The length of interconnect is taken as 4mm and far end capacitive loading is 30 fF. The SPICE waveforms are generated at far end of victim line for varying width of aggressor driver PMOS from 20μm to 120μm in steps of 20μm. The corresponding NMOS width is half of PMOS. The victim driver width is kept fixed at 40μm for PMOS and 20μm for NMOS. The simulation is carried out at 0.13μm, 1.5V technology node. Three different cases of input switching are considered. It is observed that level of crosstalk noise for static and dynamic switching of victim line increases with driver width.

Impact of driver size and interwire parasitics on crosstalk noise and delay

Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and...

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Purpose – This paper aims to address the various issues of board‐level (off‐chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off‐chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted.Design/methodology/approach – The problems in board‐level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board‐level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique.Findings – The dominant‐1 (wired‐OR, denoted as WOR), dominant‐0 (wired‐AND, denoted a...