Manoj Kumar Majumder

Analysis of MWCNT and Bundled SWCNT Interconnects: Impact on Crosstalk and Area

Multiwalled carbon nanotube (MWCNT) and bundled single-walled carbon nanotube (SWCNT) interconnect have provided potentially attractive solution in current deep submicrometer and nanoscale technology. This letter presents a comparative analysis between the MWCNT and the bundled SWCNT at different global interconnect lengths in terms of crosstalk-induced time delay and area by using a three-line-bus architecture. Each line of the bus architecture is replaced by the RLC models of the MWCNT and bundled-SWCNT interconnects. The crosstalk-induced time delay is predicted at the middle line (victim) when the other two lines (aggressors) are switched in the opposite direction. From HSPICE circuit simulation results, it has been observed that the overall improvement in the delay is 52.4% more for the MWCNT as compared with the equivalent bundled-SWCNT interconnects. Consequently, on an average, the MWCNT requires 97.8% lesser area as compared with the bundled-SWCNT interconnects for the same crosstalk-induced time delay.

Analysis of Delay and Dynamic Crosstalk in Bundled Carbon Nanotube Interconnects

Mixed carbon nanotube bundles (MCBs) are considered to be highly potential interconnect solutions in the current nanoscale regime. Different MCBs with random and spatial arrangements are proposed based on the placements of single- and multiwalled carbon nanotubes (CNTs) (SWNTs and MWNTs) in a bundle. Propagation delay and dynamic crosstalk performances are analyzed using the modified equivalent single conductor model of proposed MCB topologies. Encouragingly, a significant reduction in propagation delay and crosstalk delay is observed for a spatial arrangement of an MCB wherein MWNTs are placed peripherally to the centrally located SWNTs. Typically, the average delay with and without crosstalk is improved by 82.8% and 80%, respectively, compared to the MCB having randomly distributed SWNTs and MWNTs.

Time and Frequency Domain Analysis of MLGNR Interconnects

Multilayer graphene nanoribbons (MLGNRs) have potentially provided attractive solutions in an intensely growing researched area of interconnects. However, for MLGNR interconnects, the doping is inevitable since the conductivity of neutral MLGNR is much lower than even Cu. Therefore, a doped MLGNR can potentially exhibits smaller resistance in comparison to Cu wires. This paper analyzes and compares the power, delay, and bandwidth performance of Cu and doped MLGNR using an equivalent single conductor model. For similar dimensions, the overall delay and power dissipation of doped MLGNR is substantially smaller by 86.13% and 43.72%, respectively, in comparison to the Cu interconnects. Moreover, MLGNR demonstrates prominently improved bandwidth and relative stability at global interconnect dimensions. However, a narrow width MLGNR in a realistic scenario exhibits rough edges that significantly reduces the mean free path and, thereby, raises its resistance. Considering these facts, this paper for the first time analyzes and compares the performance of Cu and MLGNR interconnects with different edge roughness conditions.

Graphene Based On-Chip Interconnects and TSVs : Prospects and Challenges

In the first four decades of the semiconductor industry, the system performance was entirely dependent on transistor delay and power dissipation. With technology scaling, the transistor delay and power dissipation significantly reduced; however, a negative impact on the interconnect performance was realized. The reduction in the cross-sectional area of copper (Cu) interconnects resulted in higher resistivity under the effects of enhanced grain and surface scattering. Moreover, with smaller interconnect dimensions and higher operating frequency, the performance of Cu interconnects is gradually being limited by the electromigration effect, stability, operational bandwidth, and crosstalk. This trend is forcing researchers to find an alternative solution for high-speed very-large-scale integration (VLSI) interconnects.

Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects

Abstract Multi-walled carbon nanotube (MWCNT) bundles have potentially provided attractive solution in nanoscale VLSI interconnects. In current fabrication process, it is not trivial to grow a densely packed bundle having MWCNTs with similar number of shells. A realistic nanotube bundle, in fact, is a mixed CNT bundle consisting of MWCNTs of different diameters. This research paper presents an analytical model of mixed CNT bundle wherein MWCNTs having different number of shells are densely packed. Two different types of MWCNT bundles are presented: (1) MB that contains MWCNTs with similar number of shells (i.e., uniform diameters) and (2) MMB wherein MWCNTs having different number of shells (i.e., non-uniform diameters) are mixed. Multi-conductor transmission line theory is used to present an equivalent single-conductor (ESC) model of different MB and MMB configurations. Using the ESC model, performance is analyzed to address the effect of propagation delay, crosstalk and power dissipation that explores the reliability of an interconnect wire. It is observed that using an MMB arrangement, the overall reduction in delay and crosstalk are 15.33% and 29.59%, respectively, compared to the MB for almost similar power dissipation.

Carbon Nanotube: Properties and Applications

This chapter presents the unique atomic structure and properties of carbon nanotube (CNT). The electronic band structure of carbon nanotube along with their small size and low dimension are responsible for their unique electrical, mechanical, and thermal properties. This chapter summarizes the electronic band structure of one-dimensional CNTs, various transport properties, and their real-world applications. Additionally, a brief about the production and purification of CNTs is also presented in this chapter.

Carbon Nanotube Based 3-D Interconnects - A Reality or a Distant Dream

A 3D IC is a chip having multiple tiers of stacked dies. The vertically stacked dies are electrically connected through 3D/vertical interconnects or popularly known as through-silicon-vias (TSVs). Development of a reliable 3D integrated system is largely dependent on the choice of filler material used in the TSV. Although, several researchers and fabrication houses have demonstrated the usage of copper as filler material, but, over the time it would suffer due to the rapid increase in resistivity under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of a highly diffusive barrier layer. However, these limitations can be overcome by CNTs that exhibit higher mechanical and thermal stability, higher conductivity and larger current carrying capability. Moreover, a bundle of CNT conducts current parallely that drastically reduces the resistive parasitic and thereby propagation delay. Thus, bundled CNTs can be predicted as one of the potential candidates for future high-speed TSVs. However, the CNT growth temperature is greater than 600?A 3D IC is a chip having multiple tiers of stacked dies. The vertically stacked dies are electrically connected through 3D/vertical interconnects or popularly known as through-silicon-vias (TSVs). Development of a reliable 3D integrated system is largely dependent on the choice of filler material used in the TSV. Although, several researchers and fabrication houses have demonstrated the usage of copper as filler material, but, over the time it would suffer due to the rapid increase in resistivity under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of a highly diffusive barrier layer. However, these limitations can be overcome by CNTs that exhibit higher mechanical and thermal stability, higher conductivity and larger current carrying capability. Moreover, a bundle of CNT conducts current parallely that drastically reduces the resistive parasitic and thereby propagation delay. Thus, bundled CNTs can be predicted as one of the potential candidates for future high-speed TSVs. However, the CNT growth temperature is greater than 600°C that is unfortunately incompatible with CMOS devices and many other temperature-sensitive materials, therefore, the manufacturing of CNTs largely depends on the success of fabrication houses.C that is unfortunately incompatible with CMOS devices and many other temperature-sensitive materials, therefore, the manufacturing of CNTs largely depends on the success of fabrication houses.

Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect

In this paper, a more realistic analytical model for randomly distributed mixed carbon nanotube (CNT) bundle (MCB) is presented for the analysis of crosstalk induced delay. Several researchers have proposed analytical models for interconnects based on single-walled CNT (SWCNT), multi-walled CNT (MWCNT) bundle and most interestingly, spatially arranged mixed CNTs. Although, bundled SWCNTs and MWCNTs are easily realizable, but, practically it is almost impossible to fabricate a MCB with precise arrangements of SWCNTs and MWCNTs. Motivated by these facts, this paper presents a corner placement algorithm for randomly distributed SWCNTs and MWCNTs of different diameters in a MCB. The performance of MCB is compared with that of conventional bundled SWCNT and bundled MWCNT at different coupled interconnect lengths and spacing. Encouragingly, for a fixed cross-sectional area, the overall crosstalk induced delay of MCB reduces by 65.03% and 23.54% in comparison to the bundles having either SWCNTs or MWCNTs with smaller diameters, respectively. However, in contradiction to most of the previously reported results, bundled MWCNTs with larger diameters outperform the randomly distributed MCBs in terms of crosstalk performance.

Comparison of propagation delay in single- and multi-layer graphene nanoribbon interconnects

Multi-layer graphene nanoribbons (MLGNRs) have potentially provided attractive solution over single-layer GNR (SLGNR) interconnects. This research paper presents an equivalent RLC model for GNR interconnects to study the effect of propagation delay. A driver-interconnect-load (DIL) system employing CMOS driver is used to analyze the performance. It has been observed that the overall delay performance is improved by 94.5% for MLGNR as compared to SLGNR.

Carbon Nanotube Based VLSI Interconnects

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