Dharmendar Reddy

Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current-voltage characteristics. Advantages over CMOS in terms of lower voltage and power are discussed.

Graphene for CMOS and Beyond CMOS Applications

Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated with room temperature field-effect mobilities close to 10 000 cm2/Vs. But since graphene is a gapless semiconductor, these transistors have high off-state leakage and nonsaturating drive currents. This is problematic for digital logic, but is acceptable for analog device applications such as low-noise amplifiers and radio-frequency (RF)/millimeter-wave field-effect transistors (FETs). The remarkable transport physics of graphene due to its linear bandstructure have led to novel beyond CMOS logic devices as well, such as “pseudospin” devices.

Current saturation in submicrometer graphene transistors with thin gate dielectric: experiment, simulation, and theory.

Recently, graphene field-effect transistors (FET) with cutoff frequencies (f(T)) between 100 and 300 GHz have been reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance (g(ds)= dI(ds)/dV(ds)). A crucial figure-of-merit for analog/RF transistors is the intrinsic voltage gain (g(m)/g(ds)) which requires both high g(m) (primary component of f(T)) and low g(ds). Obtaining current saturation has become one of the key challenges in graphene device design. In this work, we study theoretically the influence of the dielectric thickness on the output characteristics of graphene FETs by using a surface-potential-based device model. We also experimentally demonstrate that by employing a very thin gate dielectric (equivalent oxide thickness less than 2 nm), full drain current saturation can be obtained for large-scale chemical vapor deposition graphene FETs with short channels. In addition to showing intrinsic voltage gain (as high as 34) that is comparable to commercial semiconductor FETs with bandgaps, we also demonstrate high frequency AC voltage gain and S21 power gain from s-parameter measurements.

Bilayer Pseudospin Field-Effect Transistor: Applications to Boolean Logic

We have recently proposed a new type of bilayer graphene-based transistor for ultralow-power (perhaps 1000 times less compared with CMOS) room-temperature operation, namely, the bilayer pseudospin field-effect transistor (BiSFET). BiSFET operation is based on gated exciton-condensate-enhanced tunneling. Here, we discuss implementation, operation, and predicted power consumption of BiSFET-based Boolean logic gates, including an inverter, an inverter-based nor gate, and a programmable nand/or, as well as a BiSFET-based memory element. The advantages over CMOS in terms of lower voltage and power are discussed.

Bilayer graphene vertical tunneling field effect transistor

Electronic devices have been explored in the past based on resonant single-electron CB (conduction band) to CB tunneling between parallel quasi-two dimensional (2D) quantum wells within III-V heterostructures and their accompanying negative differential resistance (NDR) [1]. Such devices are attractive for high speed electronics, and digital logic circuits also have been demonstrated using a combination of conventional and such NDR FETs [2]. For two graphene layers separated by a tunnel barrier, we recently proposed the ultra-low-voltage Bilayer pseudoSpin FET (BiSFET) which would employ enhanced nonresonant VB (valence band) to CB tunneling, with a nevertheless very sharp NDR characteristic based on a predicted room-temperature many-body superfluid state [3]. However, NDR due to resonant single-particle CB-to-CB or VB-to-VB tunneling may also be achievable in such a structure. Furthermore, the atomically near-perfect 2D nature of the component graphene layers and the conduction/valence band symmetry may offer advantages over III-Vs. Here, we model the I-V characteristics due to single-particle tunneling in such a structure, Fig. 1, using a perturbative tunneling Hamiltonian approach [4,5], and deviations from this simple theory using atomistic tight-binding nonequilibrium Greens function (NEGF) simulation.

Bilayer pseudoSpin field effect transistor (BiSFET): A proposed logic device and circuits

We have recently proposed a new type of gated bilayer graphene-based transistor based on many-body tunneling, for ultra-low power (perhaps 1000 X compared to CMOS) room temperature operation [1]. The physics of this system can be addressed by treating the layer (top and bottom) degree of freedom as a pseudospin, much like spin (up and down) in a ferromagnet (Fig. 1). Electrons in one layer of a bilayer system can pair with holes in the opposite layer resulting in electron-hole-pairs/excitons (bosons) which then can condense and induce coherence between the layers, effectively shorting them through a many-body tunneling current at low interlayer bias, even when the single-particle tunneling current is small [2]. This Bose condensate current has been observed experimentally only in GaAs/AlGaAs bilayer systems at very low-temperatures and under high magnetic fields [2,3]. It has been predicted recently, however, that this condensate could occur possibly above room temperature absent magnetic fields in an n-type and p-type graphene layer pair due to a unique synergy of graphene properties: carrier confinement to a single atomic layer, symmetric electron-hole band structures, very low density of states, and no bandgap [4,5].

CMOS and Beyond: Bilayer pseudospin field effect transistor

Introduction The bilayer pseudospin field effect transistor (BiSFET) is intended to enable much lower voltage and power operation than possible with complementary metal–oxide–semiconductor (CMOS) field effect transistor (FET)-based logic [1, 2]. The ultimate limits of CMOS are not due to fabrication technology limitations. Rather, they are intrinsic to its operating principles, defined by basic physics such as charge carrier thermionic emission over the channel barrier and quantum mechanical tunneling through it. New operating principles are required. The BiSFET relies on the possibility of room temperature excitonic (electron-hole) superfluid condensation in two dielectrically separated graphene layers [3, 4]. While the physics is interesting in its own right, from the device point of view this many-body physics brings with it the possibility of a strong sensitivity to sub-thermal voltages (sub- k B T / q voltages, where k B is Boltzmann’s constant, T is the temperature in Kelvin, and q is the magnitude of electron charge) in the current–voltage ( I – V ) characteristics [5–7]. With power consumption proportional to the square of voltage, use of voltages on the scale of or less than room temperature k B T / q ≈ 26 mV offers order of magnitude reductions in switching energies as compared to even end-of-the roadmap CMOS [8]. Circuit simulation with 25 mV power supplies show switching energies on the scale of 10 zeptojoules (zJ) per BiSFET (where 1 zJ = 10 –21 J = 10 –3 aJ)! However, with this potential for voltage reduction also come I – V characteristics much different from those of MOSFETs that must be worked around at worst, and may provide new circuit opportunities at best. In terms of interconnects, information would continue to be passed via charge among devices. In this way, BiSFETs would also be compatible with existing electronic devices after voltage level shifts.

From Coherent States In Adjacent Graphene Layers Toward Low-Power Logic Circuits

Colleagues and we recently proposed a new type of transistor, a Bilayer PseudoSpin Field Effect Transistor (BiSFET), based on many-body coherent states in coupled electron and hole layers in graphene. Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineerable device parameters on the formation and gating of interlayer coherent state.

Novel double layer graphene transistors-bilayer pseudospin FETs and 2D-2D tunnel FETs

In this paper, bilayer pseudospin FET (BiSFET) is fabricated and tested for the condensate using Coulomb drag measurements in the double layer graphene system. The basic BiSFET structure can also be used as 2D-2D single particle tunnel FET, and the single particle h-h and e-e 2D-2D tunnel FETs, which is graphenes single-atom thickness could lead to more ideal interlayer tunneling characteristics provided the layers can be aligned. Single particle tunneling current calculations have been performed which show NDR characteristics, reminiscent of the BiSFET, albeit with higher operating powers.