Didier Rene Haspeslagh

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, /spl Sigma//spl Delta/ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order /spl Sigma//spl Delta/ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 /spl mu/m CMOS circuit measures 65 mm/sup 2/ and consumes 1.9 W from a single 5 V power supply.

An analog radio front-end chip set for a 1.9 GHz mobile radio telephone application

A single-chip BiCMOS analog radio for mobile telephony is a strategic utopia today because few foundries provide a BiCMOS technology with sufficient bipolar f/sub T/ for the low-noise mixers in the receiver and transmitter phase modulators and demodulators at 1.9 GHz. The solution presented in this paper is to use an RF silicon bipolar chip for the high frequency circuits of the transceiver and synthesizer and standard low cost CMOS for low-frequency transceiver analog signal processing and synthesizer functions.<<ETX>>

A highly linear CMOS Gm-C bandpass filter for video applications

A 14th order CMOS transconductance-C (Gm-C) bandpass filter for video applications is described. By using highly linear Gm-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured IM3 @ 600 kHz is -61 dB for a 4 Vpp input signal. On-chip automatic frequency tuning provides more than 300% center frequency range of the filter with 1% frequency accuracy. The 0.7 /spl mu/m CMOS filter measures 4.8 mm/sup 2/ and consumes 70 mW from a single 5 V power supply.

A CMOS differential buffer amplifier with accurate gain and clipping control

A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realised in a 1.2 um CMOS process with a single 5 V power supply. Measurements confirm the presented techniques.

A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI

A general-purpose modular-based scan chain between the analog-digital boundary of a mixed analog/digital design is proposed. This general-purpose Design-For-Test methodology is oriented towards the test of the mixed-signal modules within the design. Implementing this structure improves the controllability and observability of these modules and the reusability of the test software at a minimum cost.

A four-channel digital signal processor in 1.2- mu m CMOS with on-chip D/A and A/D conversion serving four speech channels in a new-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2- mu m CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm/sup 2/ 1.2- mu m CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/ mu -law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting. >

Wireless telecom silicon integration: analog design for radio, baseband and speech spectrum

The application today, pushing analog design for CMOS and RF‐bipolar into new frontiers is definitely the mobile radio telephony. New telecom systems like GSM, PCN, DECT, DCS, Wireless in the loop ... are all developing very rapidly and will enable us very soon to organise a complete telephone network with full coverage for your car, as well as in your kitchen and on your office desk. In Europe the major telecom companies have worked together to establish one common standard for cellular mobile radio communications at 900 MHz. Similar things are happening for other wireless personal communication systems. Basically the cellular radio telephone, the wireless PABX and the wireless SLIC are bringing the same challenges to analog circuit design: maximum integration of the basic radio functions into 1 or 2 silicon chips, CMOS, Bipolar or BiCMOS or GaAs. The analog circuit designer for radio telephone applications will need all the state of the art analog design know‐how available today, from RF‐mixers and GHz range low noise amplifiers and local oscillator synthesizers over base band 100 kHz CMOS analog to low frequency speech analog to digital conversion. And for all these circuits the message is: minimum power consumption for battery autonomy, minimum silicon area for maximum functional integration per die to obtain a small, low cost pocket size radio telephone.

A 4/7 kHz audio bandwidth selectable digital phone interface (DPI) chip with on-chip analog functions and modem

The Digital Phone Interface (DPI) is designed for a new generation of digital telephone terminals for private exchanges. This circuit gives a total solution for all telephone function thereby including DSP functions, voice coding/decoding and analog front end, signal generators for DTMF and ringing, modem for data transfer between terminal and exchange and a multitude of interfaces to communicate to the external world. Besides the normal earpiece micro and speaker, handsfree operation is available by using a selectable input low noise microphone amplifier and an additional 50 ¿ 100mW LS driver. For the handsfree operation an AGC and anti-oscillation (anti-larsen) function is implemented. The line modem generates a modified RTZ (WAL2) code and is able to cover distances to 1.5 km. In addition the component is extensible with external signal processing modules (echo cancelling ..) and is also able to transfer a 7 kHz speech bandwidth. The device is a mixed analog/digital design produced in a 1.2¿m CMOS technology on 46 mm2 die area and consumes 200 mW.

Ensemble de composants VLSI pour équipements GSM

RésuméLe système de radiotéléphone groupe spécial mobile (gsm)est aujourďhui opérationnel dans plusieurs pays ďEurope. ľintroduction ďun tel système a demandeéaux constructeurs ľéquipements de radiotéléphonie de très importants investissements, en particulier au niveau technologique. Après une présentation de ľarchitecture ďun terminal gsm,cet article présente les composants spécifiques développes par Alcatel pour son terminal portatif. Ces développements sont illustrés par la description de composants représentatifs de ľarchitecture,des méthodes et technologies utilisées par Alcatel. Une analyse des voies ďoptimisation futures de ces composants conclut cet article.AbstractThe gsmcellular system (global system for mobile) is now open in many European countries. The introduction of such a system has requested for the manufacturers very important investments, particularly technological investments. Beginning with the description of the architecture of a gsmterminal, the paper presents the specific components developped by Alcatel for its handportable terminal. These developments are detailed by the description of some of these components which are representative of the architecture, methods and technologies used by Alcatel. An analysis of future directions for the optimization of these components ends this paper.

A single chip mixed digital/analog signal processor in 1.2 mu CMOS interfacing 4 analog subscriber lines to the PCM digital System 12 exchange

For the development of a new generation line circuit a 4 channel speech processor was designed and fabricated in a 1.2 mu CMOS technology. The circuit includes digital signal processing for receive and transmit signals as well as the analog frontend interfacing four subscriber lines to a PCM digital exchange. The device is operating on a single 5 V power supply.<<ETX>>