Markus Schimper

A fully digital multimode polar transmitter employing 17b RF DAC in 3G mode

The constantly growing quest for global roaming with a fast mobile internet access has further increased demand for multiband 3G cell phones supporting also 2G/2.5G standards, in order to provide full coverage any time, any place. In order to substantially reduce cost and size of the multimode, multiband handsets, it is necessary to develop a transmitter architecture that enables use of a multimode, multiband power amplifier, a key prerequisite to substantially reduce the number of external components, pins count, and PCB area, while at the same time significantly lowering power consumption.

A 3mW continuous-time /spl Sigma//spl Delta/-modulator for EDGE/GSM with high adjacent channel tolerance

A continuous-time 4th-order multi-bit /spl Sigma//spl Delta/-modulator for GSM/EDGE is presented. By introduction of a direct feed-forward path from the input to the quantiser, high immunity to adjacent channel interferers is achieved. The dynamic range is 90 dB (>14-bit) over a 240 kHz signal bandwidth. Accurate modelling allows optimisation of excess loop delay, thus yielding a very low power consumption of 3 mW at 1.25 V supply voltage. The modulator is clocked at 26 MHz (oversampling ratio=54). It occupies 0.5 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology.

A configurable cascaded continuous-time ΔΣ modulator with up to 15MHz bandwidth

A reconfigurable cascaded continuous-time 3–1 ΔΣ modulator with low PVT sensitivity was developed and implemented in 65nm digital CMOS. The 0.17mm2 chip achieves 67/55dB SNR and 70/61dB DR at 10/15MHz bandwidth with only 208MHz clock frequency and 10.5mW power consumption from a 1.3V supply.