Dieter K. Schroder

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization.

Solar cell contact resistance—A review

An overview of ohmic contacts on solar cells is presented. The fundamentals of metal-semiconductor contacts are reviewed, including the Schottky approach, Fermi level pinning by surface states, and the mechanisms of thermionic emission, thermionic/field emission, and tunneling for current transport. The concept of contact resistance is developed and contact resistance data for several different contact materials on both silicon and gallium arsenide over a range of doping densities are summarized. Finally, the requirements imposed by solar cells on contact resistance are detailed.

Carrier lifetimes in silicon

Carrier lifetimes in semiconductors are being rediscovered by the Si IC community, because the lifetime is a very effective parameter to characterize the purity of a material or device. It has become a process and equipment characterization parameter. The various recombination mechanisms are discussed and the concept of recombination and generation lifetime is presented. We show that surface recombination/generation plays an important role in todays high purity Si and will become yet more important as bulk impurity densities in Si are reduced further. Furthermore, the dependence of lifetime on impurity energy level and minority carrier injection level is discussed. Concepts are stressed in the paper, with the necessary equations to clarify these concepts. Wherever possible, the concepts are augmented with experimental data, with particular emphasis on the case of iron in silicon, because Fe is one of the most important impurities in Si today. We have used Si in the examples because lifetime measurements are most commonly made in Si.

Negative bias temperature instability: What do we understand?

Abstract We present a brief overview of negative bias temperature instability (NBTI) commonly observed for in p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) when stressed with negative gate voltages at elevated temperatures and discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss some of the models that have been proposed for both NBTI degradation and recovery and p- versus n-MOSFETs. We also address the time and energy dependence effects of NBTI and crystal orientation. Finally we mention some aspect of circuit degradation. The general conclusion is that although we understand much about NBTI, several aspects are poorly understood. This may be due to a lack of a basic understanding or due to varying experimental data that are likely the result of sample preparation and measurement conditions.

gettering in silicon

A series of gettering experiments have been carried out for a better understanding of gettering mechanism(s) in silicon. We find that oxidation and oxynitridation, which are known to inject silicon interstitials, do not getter metallic impurities such as Au, Cu, Fe, and Ni while phosphorus (P) diffusion does produce effective gettering of these metals. We also find from P diffusion, Ar ion implantation, and Ni film gettering performed as a function of temperature, there exists an optimum gettering temperature. From a comprehensive discussion of the existing models, we conclude that neither the enhanced metal solubility nor the silicon interstitial model explains our experimental results. Furthermore, it is shown that generation of dislocations is not a prerequisite for effective gettering. A model, based on the segregation of impurities at high temperatures and on the release/diffusion of metallic impurities at lower temperatures, is proposed to explain all of our results. A general form of the segregatio...

Surface voltage and surface photovoltage: history, theory and applications

Surface voltage and surface photovoltage measurements have become important semiconductor characterization tools, largely because of the availability of commercial equipment and the contactless nature of the measurements. The range of the basic technique has been expanded through the addition of corona charge. The combination of surface charge and illumination allows surface voltage, surface barrier height, flatband voltage, oxide thickness, oxide charge density, interface trap density, mobile charge density, oxide integrity, minority carrier diffusion length, generation lifetime, recombination lifetime and doping density to be determined. In this review I shall briefly review the history of surface voltage, then discuss the principles of the technique and give some examples and applications.

The concept of generation and recombination lifetimes in semiconductors

The purpose of this brief is to discuss the concept of generation and recombination lifetimes, a concept frequently confused in the literature. The regimes of device operation where they apply is discussed and it is shown experimentally for the first time that the two can be very different in magnitude.

Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM

The degradation of thin tunnel gate oxide under constant Fowler-Nordheim (FN) current stress was studied using flash EEPROM structures. The degradation is a strong function of the amount of injected charge density (Q/sub inj/), oxide thickness, and the direction of stress. Positive charge trapping is usually dominant at low Q/sub inj/ followed by negative charge trapping at high Q/sub inj/, causing a turnaround of gate voltage and threshold voltage. Interface trap generation continues to increase with increasing stress, as evidenced by subthreshold slope and transconductance. Gate injection stress creates more positive charge traps and interface traps than does substrate injection stress. Oxide degradation gets more severe for thicker oxide, due to more oxide charge trapping and interface trap generation by impact ionization. A simple model of oxide degradation and breakdown was established based on the experimental results. It indicates that the damage in the oxide is more serious near the anode interface by impact ionization and oxide breakdown is also closely related to surface roughness at the cathode interface. When all the damage sites in the oxide connect and a conductive path between cathode and anode is formed, oxide breakdown occurs. The damage is more serious for thicker oxide because a thicker oxide is more susceptible to impact ionization.

Recombination properties of oxygen‐precipitated silicon

It is well known that recombination lifetimes are significantly degraded in oxygen‐precipitated silicon. The possible sources for lifetime degradation are expected to be oxygen precipitates (OP’s), dislocation loops, stacking faults, and point defects associated with self‐interstitials generated during the oxygen precipitation process. From the results of an extensive experimental study using IR absorption, TEM, DLTS, and SPV (surface photovoltage), we have found that OP’s are mainly responsible for the observed lifetime degradation and that recombination at OP’s takes place through Si/OP interface states. In addition we have observed that the lifetime degradation is more severe in p‐Si than in n‐Si even for identical densities and sizes of OP’s. A model for recombination at OP’s is presented in terms of the surface recombination velocity at the Si/OP interface and their average density and size. To explain the lifetime difference between n‐Si and p‐Si we propose a band bending around OP’s caused by posit...

Scaled silicon MOSFETs: degradation of the total gate capacitance

We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N/sub s/=N/sub s/(VG) characteristics of the device toward lower gate voltages.