Kuntal Joardar

A simple approach to modeling cross-talk in integrated circuits

A simple engineering approach for rapid simulation of cross-talk in mixed-mode ICs using SPICE is presented. A side-by-side comparison of several cross-talk reduction schemes has shown that while an SOI-based process provides high isolation from cross-talk at low operating frequencies, its benefit is lost at high frequencies. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. Lumped parameter equivalent circuits have also been developed to represent different isolation schemes in SPICE. The isolation characteristics of test structures employing the above techniques are computed using SPICE and the results compared with two-dimensional device simulation. The results are also compared with experimental measurements on actual silicon to validate the models. >

An improved MOSFET model for circuit simulation

Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model.

Signal isolation in BiCMOS mixed mode integrated circuits

Comparing several cross-talk reduction schemes using two-dimensional device simulation and measurements on silicon has shown that while SOI based processes provide high isolation from cross-talk, fully junction isolated wells can provide equal or better cross-talk immunity at a lesser expense. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. A lumped parameter equivalent circuit has also been developed to simulate fully junction isolated wells in SPICE.

Substrate crosstalk in BiCMOS mixed mode integrated circuits

Abstract A comparison of several crosstalk reduction schemes using two-dimensional device simulation and measurements on silicon has shown that while SOI based processes provide high isolation from crosstalk, fully junction isolated wells can provide equal or better crosstalk immunity at a lesser expense. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. A lumped parameter equivalent circuit has also been developed to simulate fully junction isolated wells in SPICE.

An improved analytical model for collector currents in lateral bipolar transistors

Detailed analyses of the lateral bipolar transistor have been performed and a physically based model for the collector current developed. Hybrid mode operation of the lateral BJT in the presence of a gate electrode has been considered. Two-dimensional current flow in the base has also been taken into account without the use of empirical parameters. Comparisons with numerical simulations, existing models, and experimental data have been performed to demonstrate the accuracy and improvements realized by the new model. >

A Physically-Based Compact Model for LDMOS Transistors

This paper presents a physically based model for LDMOS transistors. The model advances the state-of-the-art by using a formulation applicable across a wide voltage range, by accounting for the distributed parasitic metal effects, and by properly modeling the bias dependence of parasitic capacitances. The model is implemented in Motorola’s internal simulator MCSPICE.

A new technique for measuring junction capacitance in bipolar transistors

A new methodology for measuring p/n junction capacitance is demonstrated. The method is dc based making it suitable for use in automated high volume measurements. The validity of the technique is supported by both simulated and experimentally measured data.

Nano-scale Recessed Asymmetric Schottky Contacted CMOS

A new CMOS device architecture named as Recessed Asymmetric Schottky Contacted CMOS ( RASC-CMOS) has been proposed and simulated by using commercial version device simulator DESSIS 6.1. RASC-CMOS can eliminate the two critical drawbacks of conventional Schottky contacted CMOS (SC-CMOS): 1) unacceptable off-state current (>10 nA//spl mu/m), 2) strong short-channel effects when the feature size of SC-CMOS scaled down to 10 nm. In the meantime, RASC-CM0S has kept the advantage of with extremely simplified fabrication process of SC-CMOS.

Analysis of the small-signal voltage decay technique in the characterization of Si concentrator solar cells

Detailed analyses of the small-signal voltage decay (SSVD) method of lifetime measurement have been performed. The main difficulty in voltage decay techniques is that the boundary conditions at the junction are coupled. A solution to the time-dependent diffusion equations has been obtained using the quasi-static emitter (QSE) approximation. Assuming a power-law emitter doping profile, a solution to the coupled diffusion equations has also been obtained using a dynamical approach without the QSE approximation. The extent to which effects such as emitter recombination and bandgap narrowing affect the SSVD lifetime has been examined using this solution. The SSVD technique has been applied in investigating the variation of minority-carrier recombination rates in the emitter, base, and back surface of concentrator solar cells with illumination intensities. The experimentally observed degradation in SSVD lifetime with increasing illumination intensity has been accounted for quantitatively. >

An analytical model for collector currents in gated lateral bipolar transistors

A physically based, analytical model for collector currents in lateral bipolar junction transistors is presented and used to describe the hybrid mode operation of these devices in the presence of a gate electrode over the base region. Results obtained from the analytical model are compared with those of computer simulations. Good agreement has been demonstrated with both numerical simulations and experimental data.<<ETX>>