Dietmar Straeussnigg

A 350MHz low-OSR /spl Delta//spl Sigma/ current-steering DAC with active termination in 0.13 /spl mu/m CMOS

A time-interleaved architecture overcomes the dynamic performance limitations of standard DWA switching. Clocked at 350MHz, the DAC with active output buffer achieves a linearity of 76dB for a signal swing of 1.536V and an effective resolution of 11.9b in a bandwidth of 29.16MHz. It is fabricated in a standard 0.13 /spl mu/m CMOS process and consumes 62mW from a 1.5V supply.

Comparative study of linear and non-linear integrated control schemes applied to a Buck converter for mobile applications

Energy-efficient conversion of DC voltages is gaining more and more importance in low-power applications, especially in mobile and wireless systems. Several control techniques can be applied to achieve output regulation of a Buck DC-DC converter. In this paper a linear PID (proportional-integral-derivative) control loop, both in analog and digital domain, is derived and its performance is compared to a non-linear regulation loop based on the sliding-mode theory. A goal of this paper is to point out potential advantages and drawbacks of the different solutions. This exploration forms the starting point for the implementation of the most promising concepts in a 65 nm CMOS technology.

SystemC-AMS modeling and simulation of digitally controlled DC-DC converters

In this paper, an innovative method to model and simulate DC-DC converters with a digital or mixed-signal control loop is proposed using the SystemC-AMS hardware-description language. The proposed method was employed to model a specific test case, consisting of a Buck converter with a digital PID regulator. The reliability of the model was checked by comparing the results with MATLAB/Simulink simulations. The SystemC-AMS approach was found to be well suited to model the proposed system and very efficient from a computational point of view, since the simulation time can be strongly reduced with respect to other solutions (e.g. MATLAB/Simulink).

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator

Capacitive or resistive sensors can be included in the feedback network of an oscillator to implement a data acquisition system. A higher sampling rate, compared with standard oversampled converters, is required to maintain a sufficient SNR in this case. In this paper, we propose an architecture based on a LC-CMOS oscillator and a digital interface that can be completely integrated on chip and satisfies low clock specifications of standard microphone capacitive interfaces. The complete system outputs one-bit bitstream at 15.53MHz and achieves SNR of 55.38dB for -26dBfs input tone.

9.5 A 1.8V true-differential 140dB SPL full-scale standard CMOS MEMS digital microphone exhibiting 67dB SNR

Over the last few years, robust MEMS microphones have gained significant market share in consumer applications such as mobile phones and hearing aids. The consumer market is demanding improved quality for audio recording, while also being capable of suppressing high-energy disturbers, e.g., wind noise. The challenge is to achieve both high DR and SNR at low supply voltages that limit signal swing. Signal levels are expressed in dB Sound-Pressure-Level (dB SPL) with respect to the human hearing threshold at a sound pressure of 20µPa corresponding to 0dB SPL. Todays mass-market MEMS digital microphone solutions typically process sound up to 120dB SPL [1,2].

Signal boosting to extend the bandwidth of oversampled converters

This paper presents a novel technique to extend the bandwidth of oversampled Analog-to-Digital Converters and a method to optimize their design to avoid instability, when oversampling has to be preserved and clock frequency cannot be increased. This proposal allows the converter to increase the resolution only introducing minor circuit modifications when processing input signals in the extended band or even in both bands concurrently is needed for different applications. The technique consists of boosting the signal in the extended band by modifying the signal transfer function of the converter and keeping the noise transfer function unaffected. An improvement of 6dB in the Signal-to-Noise Ratio is reached, which allows to maintain the order of the loop filter or the resolution of the quantizer, thus saving power consumption and silicon area.

Bandwidth extension of oversampled Analog-to-Digital converters by means of gain boosting

This paper presents a novel technique to extend the bandwidth of oversampled Analog-to-Digital Converters (ADCs) when clock frequency cannot be increased and oversampling has to be preserved. The Signal Transfer Function (STF) of the converter is modified to boost the signal in the extended band. The modification keeps the noise transfer function (NTF) unaffected, and therefore, there is no need of increasing the order of the loop filter or the resolution of the quantizer. Using the proposed technique, the converter has the capability of processing input signals in the extended band with increased resolution or even in both bands concurrently, by introducing minor circuit modifications. An improvement of 6dB in the Signal-to-Noise Ratio is reached, which allows to maintain the order of the loop filter or the resolution of the quantizer, thus saving power consumption and silicon area.

A noise coupled ΣΔ architecture using a Non Uniform Quantizer

A low power Discrete Time Sigma Delta modulator (DT SDM) for sensor applications is described in this paper. A third order noise shaping is reached with a second order loop filter due to the use of a noise coupling technique at the input of the quantizer. Using a Non Uniform Quantizer (NUQ) the hardware complexity is reduced. This architecture is suitable for high dynamic range sensor applications with some compression. Conventional mismatch shaping techniques can still be used to enhance linearity if a segmented DAC is used. At low amplitudes the NUQ is linearized by the noise coupling loop. A simulation example is presented, achieving a dynamic range of 103dB and a peak SNDR of 93dB over 25KHz bandwidth, and using a 1.6MHz clock.

A time-encoding CMOS capacitive sensor readout circuit with flicker noise reduction

This paper shows a novel capacity to digital measurement circuit that is suited for differential MEMS capacitive sensors such as pressure sensors or condenser microphones. The basic operating principle relies on two differential reactance-controlled multivibrator circuits whose frequency differences are sensed by a Time to Digital Converter. The multivibrator oscillators may be biased in the relaxation oscillation mode, where demodulated flicker noise is greatly attenuated by large scale excitation of CMOS transistors. The paper shows a system level description of the readout circuit, a full transistor design in 0.13u CMOS and an oscillator characterization form measurements on a discrete demonstration circuit.