Luca Bizjak

A digital implementation for PWM phase-frequency synchronization in SMPS systems

This paper describes a novel concept of PWM phase and frequency synchronization. This approach applies for digitally controlled switched mode power supplies (SMPS) which need to regulate the switching frequency externally. One of the well-known advantages of having a system with a controllable switching behavior is the mitigation of the Electromagnetic Interference (EMI), which leads to the system cost reduction as a smaller input filter is required. The proposed solution overcomes analog and digital state of the art drawbacks such as limitation of the synchronization frequency range, susceptibility to noise and glitches, undesired overshoots/undershoots on the output voltage and the tuning of the IC digital clock which leads to an over-constrained design. In order to confirm the synchronization performance the proposed solution is implemented as part of an SMPS controller integrated in a 130nm BCD (Bipolar-CMOS-DMOS) technology. The output voltage over/under-shoot caused by an abrupt frequency synchronization change has been analyzed and measured. The frequency and phase settling time have been characterized with respect to various configurations. The robustness against synchronization frequency and phase noise has been measured for different noise levels.