Dietrich Mund

Novel Hermetic Wafer-Level-Packaging Technology using Low-Temperature Passivation

In the past decade wafer level packaging (WLP) has been proven to be a very competitive solution regarding performance, miniaturization and costs for a wide range of applications. However, they are up to now not matching the performance of hermetically sealed Glass or Glass-to-MetalSeal packages, esp. when considering application in extreme environment. In this paper a novel packaging technology is proposed, allowing hermetic passivation and encapsulation of microelectronic devices on wafer-level. This technology combines the unique properties of microstructuring of glass on silicon process [1] with the capabilities of a wafer-level packaging technology using Silicon-Via-Contacts [2]. This new processing technology is enabling hermetic encapsulation of devices on wafer-level comprising an unique, cost effective passivation process performed at temperatures below 120°C. Wafer-Level-Packaging and Redistribution using Polymer Most of the successful wafer-level-packaging technologies introduced in the past [3,4] are using polymers as dielectric material for the passivation of microelectronic elements as well as electrical insulation of the device and the redistribution leads of the package. A broad class of materials have been developed ranging from epoxy-based materials and spin-on polymers to polyimids and BCB. Acceptable microstructuring results can be achieved with those materials by plasma etching using a photo-resist mask or by choosing a class of intrinsic photosensitive passivation polymers applying lithography directly. Generally the polymer passivation has to be cured after application to the wafer. The degree of cure of that passivation materials has a strong impact on their passivation properties and therefore on the overall reliability of the packaged electronic devices. If thermal curing is applied, Tg of the polymers is systematically lower than the bake temperature. Standard curing conditions are in the range of 160°C to 380°C for several minutes to hours depending on the polymer material. Sensitive electronic devices i.e. CMOS or analog IC’s may suffer significant loss of device performance when exposed to those curing conditions.

Evaluation of Micro Structured Glass Layers as Dielectric-and Passivation Material for Wafer Level Integrated Thin Film Capacitors and Resistors

This work describes the integration of thin micro-structured glass layers into copper / benzocyclobutene (Cu/BCB) thin film multi layer. The glass, which is deposited by a low temperature PVD-PIAD process (physical vapor deposition with plasma ion assisted deposition) using special synthesized targets, was evaluated to act as local dielectric and passivation material for integrated capacitors and resistors. Metal-insulator-metal (MIM) capacitors and micro strip resonators were realized to determine the breakdown voltage as well as the dielectric constant of the material. Furthermore the glass material was used as passivation for integrated nickel-chromium (NiCr) resistors, which were evaluated regarding their maximum applicable current density, temperature coefficient of resistance as well as long-term stability. The first chapters of this paper describe the glass deposition and structuring as well as the integration of these processes into the Cu/BCB redistribution process of Fraunhofer IZM. Afterwards the fabrication of the test structures and the results from their characterization are discussed in detail.

Wafer-Level Glass Capping as Drop-in for Miniaturized, Advanced Optical COB Packaging

The novel wafer-level packaging (WLP) process described in this paper allows quasi-hermetic capping of optical devices on wafer-level yielding miniaturized glass cavity windows on top of the optical area, at the same time leaving the contact area accessible for standard electrical connections i.e. wire bond. These smaller chip-size optical cavity packages are used within standard chip-on-board (COB) assemblies for high performance optical applications providing high yield and utmost reliability. In this paper the process flow of generating optical cavity glass wafers as well as of the wafer-level capping process is demonstrated and reliability data on wafer-level and package-level are discussed.