Volker Seidemann

Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained [1] and plasma configurations are described elsewhere [2][3]. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters.

Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices

Through-silicon-via (TSV) interconnects using the “via-last” approach are successfully applied for wafer-level packaging of complementary metal-oxide-semiconductor (CMOS) image sensors. Standard materials and processes are applied for redistribution on the backside of the devices, which is enabled by the use of plasma etched vias with tapered sidewalls. With this, high reliability for the packaged devices are achieved on component and board level. Based on the high uniformity for the via geometry in respect to the dimension of top opening, bottom opening, and sidewall angle, we discuss the coverage of those redistribution polymers and photo resists as the bases for high performance and high yield of the mature wafer-level packaging process for optical and M(O)EMS devices.

Wafer-Level Glass Capping as Drop-in for Miniaturized, Advanced Optical COB Packaging

The novel wafer-level packaging (WLP) process described in this paper allows quasi-hermetic capping of optical devices on wafer-level yielding miniaturized glass cavity windows on top of the optical area, at the same time leaving the contact area accessible for standard electrical connections i.e. wire bond. These smaller chip-size optical cavity packages are used within standard chip-on-board (COB) assemblies for high performance optical applications providing high yield and utmost reliability. In this paper the process flow of generating optical cavity glass wafers as well as of the wafer-level capping process is demonstrated and reliability data on wafer-level and package-level are discussed.