Jürgen Leib

Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained [1] and plasma configurations are described elsewhere [2][3]. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters.

Novel Hermetic Wafer-Level-Packaging Technology using Low-Temperature Passivation

In the past decade wafer level packaging (WLP) has been proven to be a very competitive solution regarding performance, miniaturization and costs for a wide range of applications. However, they are up to now not matching the performance of hermetically sealed Glass or Glass-to-MetalSeal packages, esp. when considering application in extreme environment. In this paper a novel packaging technology is proposed, allowing hermetic passivation and encapsulation of microelectronic devices on wafer-level. This technology combines the unique properties of microstructuring of glass on silicon process [1] with the capabilities of a wafer-level packaging technology using Silicon-Via-Contacts [2]. This new processing technology is enabling hermetic encapsulation of devices on wafer-level comprising an unique, cost effective passivation process performed at temperatures below 120°C. Wafer-Level-Packaging and Redistribution using Polymer Most of the successful wafer-level-packaging technologies introduced in the past [3,4] are using polymers as dielectric material for the passivation of microelectronic elements as well as electrical insulation of the device and the redistribution leads of the package. A broad class of materials have been developed ranging from epoxy-based materials and spin-on polymers to polyimids and BCB. Acceptable microstructuring results can be achieved with those materials by plasma etching using a photo-resist mask or by choosing a class of intrinsic photosensitive passivation polymers applying lithography directly. Generally the polymer passivation has to be cured after application to the wafer. The degree of cure of that passivation materials has a strong impact on their passivation properties and therefore on the overall reliability of the packaged electronic devices. If thermal curing is applied, Tg of the polymers is systematically lower than the bake temperature. Standard curing conditions are in the range of 160°C to 380°C for several minutes to hours depending on the polymer material. Sensitive electronic devices i.e. CMOS or analog IC’s may suffer significant loss of device performance when exposed to those curing conditions.

Via Interconnections for Wafer Level Packaging: Impact of Tapered Via Shape and Via Geometry on Product Yield and Reliability

The wafer level packaging for optical image sensor devices developed by Schott Advanced Packaging utilizes a through silicon via (TSV) by contacting the bond pads of the image sensors from the backside. Direct contact of the bond pads from the back side of the chip offers much shorter transmission paths to the board assemblies, thus providing faster signal speed, lower ohmic contact, efficient thermal conduction and many added advantages. After forming the vias by means of plasma etching, the electrical connection from the bottom of the via to the backside of the wafer is done by spray coating and lithography to form the redistribution layer, and prepare the wafer for bumping at a later process step. Via shape and spray coating process are the key to achieve good quality and reliable product. This paper discusses interactions between the via shape (profile angle and shape) and its effects on subsequent spray coating processes as well as its impact on electrical yield and reliability of the product. The shape of the via, and its homogeneity over the wafer significantly affect the performance and stability of the next process steps, thus careful balancing of the via forming process and the lithography are required. The impact of via morphology and via stability are also studied under production conditions on the spray coating performance.

Wafer-Level Glass Capping as Drop-in for Miniaturized, Advanced Optical COB Packaging

The novel wafer-level packaging (WLP) process described in this paper allows quasi-hermetic capping of optical devices on wafer-level yielding miniaturized glass cavity windows on top of the optical area, at the same time leaving the contact area accessible for standard electrical connections i.e. wire bond. These smaller chip-size optical cavity packages are used within standard chip-on-board (COB) assemblies for high performance optical applications providing high yield and utmost reliability. In this paper the process flow of generating optical cavity glass wafers as well as of the wafer-level capping process is demonstrated and reliability data on wafer-level and package-level are discussed.