Dimitrios N. Kouvatsos

High-performance thin-film transistors in large grain size polysilicon deposited by thermal decomposition of disilane

The characteristics of polycrystalline silicon thin-film transistors (TFTs), fabricated on films deposited in an LPCVD system using disilane, were investigated as a function of grain size. The grain size and its statistical distribution were correlated with processing conditions; optimum conditions to maximize grain size for device applications were determined. The dependence of the ON current and the OFF (leakage) current of polysilicon TFTs, as well as of their statistical distributions, on the grain size, the gate dielectric processing temperature, the channel length, and the device structure are reported and discussed. Larger grain size polycrystalline silicon films were found to yield devices with higher mobilities and lower leakage currents. TFTs, fabricated in polysilicon films with average grain sizes of 1.8 /spl mu/m with thermally grown silicon dioxide as gate dielectric, had ON/OFF current ratio well above 10/sup 8/, average effective mobility value of 170 cm/sup 2//V.s and subthreshold slope of 0.3 V/dec.

Fluorine‐Enhanced Oxidation of Silicon Effects of Fluorine on Oxide Stress and Growth Kinetics

The influence of fluorine on film stress as well as on oxide growth kinetics for oxide films grown by fluorine-enhanced thermal oxidation of silicon using NF3 as fluorine source is reported. The effect of NF3 concentration and oxidation temperature on the measured stress has been studied and compared to kinetics effects. A marked stress reduction while the oxidation rate is greatly enhanced can be observed in fluorinated oxides with respect to dry ones grown at the same temperature. This suggests a fluorine-related mechanism for stress relaxation. Moreover, a saturation of the stress relaxation with increasing fluorine exposure is observed which seems to be correlated with the saturation that we observe for the oxidation rate enhancement.

Interface State Density Reduction and Effect of Oxidation Temperature on Fluorine Incorporation and Profiling for Fluorinated Metal Oxide Semiconductor Capacitors

The effect of fluorine incorporation on the as‐grown interface state density of the system was investigated using MOS capacitors with fluorinated oxide dielectrics grown by oxidation as test structures. A clear reduction of the interface trap density, attributed to fluorine‐induced passivation of interfacial dangling bonds, weak bonds, and weak interactions, was shown for additions in the parts‐per‐million range as compared to dry oxides. Fluorine incorporation in the oxide was investigated with SIMS profiling. The application of a pulsed oxidation process in which the fluorine source is added to the oxidant in intervals within the total oxidation time demonstrated that the variation of oxidation processing parameters strongly influences the resulting fluorine profile. A two‐peak pattern of the fluorine profile, with one peak in the interfacial area and the other corresponding to the oxide area grown during the step, was observed. This pattern was strongly dependent on the oxidation temperature, with the interfacial fluorine accumulation more pronounced with increasing temperature. The pronounced influence of the oxidation temperature on the fluorine profile resulting from oxidation was ascribed to a thermally activated replacement reaction of bonded fluorine by oxygen.

An experimental study of the thermally activated processes in polycrystalline silicon thin film transistors

The thermally activated mechanisms that determine the electrical properties of polycrystalline silicon thin film transistors have been investigated. The study employed devices fabricated on long grains and different thickness polycrystalline films, which were obtained by excimer laser annealing crystallization. The transfer and the transient characteristics have been recorded and analysed in the linear operation regime. The temperature dependence of basic parameters such as leakage current, subthreshold swing and drain current overshoot transient amplitude was found to stem from the same thermally activated carriers generation mechanism. The dependence of thermally activated mechanisms on the film thickness suggests that the device operation is strongly related to polycrystalline material properties.

Influence of polysilicon film thickness on radiation response of advanced excimer laser annealed polycrystalline silicon thin film transistors

Abstract This paper presents results of gamma irradiation effects in advanced excimer laser annealed polysilicon thin film transistors realized in polysilicon films having different thicknesses. It is shown that the thickness of polysilicon film has a strong influence on the degradation level of electrical parameters of irradiated thin film transistors, offering a possibility for optimization of these devices with the purpose to increase their reliability. The analysis was performed by monitoring of important electrical parameters, as well as of the density of irradiation induced oxide trapped charge and interface traps at the oxide–polysilicon interface, and the density of polysilicon grain boundary traps in the channel region of the transistors.

SiO2 Film Stress—Thickness Dependence, Non‐Planar Oxidation, and Fluorine‐Related Effects

The thickness dependence of oxide stress for dry and fluorinated oxide films grown by NF 3 enhanced thermal oxidation was investigated. A small variation of stress with thickness was observed, Non-planar structures were oxidized and rounder corner structures were found to result in the case of fluorinated oxidation. Furthermore, pronounced oxide stress differences were observed for samples grown using two distinct fluorinated oxidation procedures and were ascribed to different fluorine profiles in the oxides

Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques

SLS ELA polysilicon TFTs fabricated in films crystallized with several novel techniques, yielding different film microstructure and texture, were investigated. The parameter statistics indicate that the TFT performance depends on film quality and asperities, in conjunction with the grain boundary trap density. The drain current transients, upon TFT switch from OFF to ON state, showed gate oxide polarization, related to film asperities and also confirmed the presence of extended defects in the TFTs of small mobilities. DC hot carrier stress was applied, indicating a reliability dependence on polysilicon structure and differences in degradation mechanisms for the various TFT technologies.

Front and Back Channel Properties of Asymmetrical Double-Gate Polysilicon TFTs

Polycrystalline silicon thin-film transistors (TFTs) with different front- and back-gate lengths are investigated. In addition, the laser annealing process yields high-quality directional grains that enable us to orient TFT channels parallel or perpendicular to the grain boundaries. It is demonstrated that the turn-on voltage is not dependent on grain orientation, unlike the subthreshold swing and the maximum transconductance. Moreover, it is shown that double-gate TFTs are fully depleted and therefore back interface properties exert critical influence on the overall TFT electrical performance. From electrical measurements the back interface state density was estimated to reach values >6 X loll cm 2 eV -1 and it was shown that the electrical performance of the double-gate devices is highly dependent on the back-to-front gate-length ratio.

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

Abstract The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V th shift. The stressing time needed for V th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I DS as stressing V DS increased, for a given on-state stressing V GS . Off-state gate–drain stressing resulted in logarithmic positive V th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.

On the importance of the Vg,max–Vth parameter on LTPS TFT stressing behavior

In this work we point out the importance of the device parameter Vg,max–Vth (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters (Vth, Gm,max, S) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar Gm,max degradation, as well as similar Vg,max–Vth evolution. Therefore, Gm,max evolution with stress time was found to be related more strongly to tail state generation, probed through Vg,max–Vth, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant Gm,max reduction could only be probed through the observation of Vg,max–Vth, a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense Gm,max degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by Vg,max–Vth evolution with stress.