C. A. Dimitriadis

Electronic properties of semiconducting FeSi2 films

Polycrystalline iron disilicide thin films are prepared by furnace annealing of electron‐beam deposited iron layers. As substrates we use single‐crystal silicon wafers, epitaxial silicon thin films on sapphire substrates, and low‐pressure chemical vapor deposited polycrystalline silicon thin films on oxidized silicon wafers. X‐ray diffraction indicates that orthorhombic β‐FeSi2 is obtained for growth temperatures in the range 800–900 °C. Photothermal deflection spectroscopy reveals a direct band‐gap of 0.85 eV. Optical transitions at energies above 1.4 eV are investigated by spectroscopic ellipsometry. Measurements of the subgap defect absorption, photoluminescence, conductivity, and of the Hall mobility suggest that lower growth temperatures yield material of better quality.

Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures

Defect properties of undoped low-pressure chemical-vapor-deposited (LPCVD) polysilicon films have been investigated by capacitance techniques on a simple metal-oxide-semiconductor (MOS) capacitor structure. The results show that the effective density of bulk and interface trap states is almost independent of the deposition pressure. After reducing the polysilicon film thickness by etching, although the grain size decreases due to the columnar mode of growth at low pressures, the trap states density reduces significantly. This finding could be explained by the hypothesis that, during the growth of the material, impurities are segregated at the film surface by fast diffusion through the grain boundaries. The transport properties of 0.5- mu m-thick polysilicon films deposited at a pressure ranging from 100 to 0.5 mtorr were evaluated from measurements on thin-film transistors (TFTs). The results demonstrate that at high pressures the grain boundaries and at low pressures the polysilicon-SiO/sub 2/ interface roughness scattering are the main factors in determining the transistor performance. >

Effect of excimer laser annealing on the structural and electrical properties of polycrystalline silicon thin-film transistors

The structural and electrical properties of excimer laser annealed polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated in relation to the laser energy density. The devices were fabricated on 50 nm thick polysilicon films prepared by excimer laser crystallization (ELA) of amorphous silicon or by a combined solid phase crystallization (SPC) and ELA process. The structural properties of the polysilicon films have been investigated by transmission electron microscopy analysis. The effective density of states distributions in the polysilicon films and in the oxide traps near the oxide/polysilicon interface have been determined from low frequency noise measurements. The TFT performance parameters are compared with respect to their correlation with the structural properties of the polysilicon films and their electrically active defects, the basic variables being the starting material (amorphous silicon or SPC polysilicon) and the laser energy density.

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poissons equation in terms of the channel length L, the silicon thickness t Si, and the gate oxide thickness t OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.

Effect of pressure on the growth of crystallites of low-pressure chemical-vapor-deposited polycrystalline silicon films and the effective electron mobility under high normal field in thin-film transistors

The morphology of polycrystalline films grown by low‐pressure chemical‐vapor deposition (LPCVD) is investigated by transmission electron microscopy (TEM) as a function of the film thickness, the deposition pressure, and the level of contamination. An orientation filtering mechanism, due to the growth‐velocity competition in the early stage of growth, is responsible for the preferred orientation of the films. The size of the crystallites, the surface roughness, and the type of the structural defects are investigated by combined cross‐sectional and plane‐view TEM analysis. In polycrystalline silicon thin‐film transistors (TFTs), the influence of surface roughness scattering on the mobility is investigated by measuring the effective electron mobility under high effective normal field at 295 and 77 K. Although the surface curvature is increased when the deposition pressure is decreased, the surface roughness scattering is constant in the deposition pressure range from 40 to 0.5 mTorr. By decreasing the deposi...

Combined electrical and mechanical properties of titanium nitride thin films as metallization materials

Titanium nitride (TiNx) thin films, ∼100 nm thick, were deposited on Si(100) substrates by dc reactive magnetron sputtering. The effects of the substrate bias voltage and deposition temperature on their optical, electrical, and mechanical properties have been studied. It was found a strong correlation between the electrical and mechanical properties of the films which are significantly improved with increasing the substrate bias voltage and the deposition temperature. The low resistivity (43 μΩ cm), combined with the high hardness and elastic modulus values, suggest the TiNx as a promising metallization material in Si technology.

Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs

A simple threshold voltage model of an undoped symmetrical double-gate MOSFET has been developed, based on an analytical solution of Poissons equation for the potential distribution. The model has been verified by comparing the threshold voltage roll-off with the channel length with simulation results for different silicon thicknesses, gate oxide thicknesses, and drain voltage values. Good agreement between model and simulation results is obtained by calibrating the minimum carrier charge sheet density adequate to achieve the turn-on condition.

Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors

In this letter, we present experimental data showing that hot-carrier stress in laser annealed polycrystalline silicon thin-film transistors provokes an anomalous turn-on voltage variation. Although under various hot-carrier stress intensities the maximum transconductance degradation shows the same power-time dependent law, turn-on voltage can exhibit different behaviors. This observation lead to the conclusion that turn-on voltage depends on two different degradation mechanisms: injection of hot carriers into the gate oxide and degradation of grain boundaries. We show that these two mechanisms may be distinguished since they obey different power-time dependent laws as a function of stress duration.

Determination of bulk states and interface states distributions in polycrystalline silicon thin‐film transistors

The field‐effect conductance activation energy Ea as a function of the gate voltage Vg is investigated for polycrystalline silicon thin‐film transistors. An analytical expression for Ea is obtained for various models of the bulk and interface states. Using a computer minimization program to fit the experimental Ea vs Vg data with the theory, the energy distribution of the bulk states and the interface states are separated for nonhydrogenated and hydrogenated polycrystalline silicon thin‐film transistors. In both cases, the bulk states have exponential band tails and a wide peak near the midgap and the interface states have an exponential distribution from the band edge.

Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements

The off-state current in n- and p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) is investigated systematically by conduction measurements at various temperatures and low-frequency noise measurements at room temperature. It is demonstrated that the leakage current is controlled by the reverse biased drain junction. The main conduction mechanisms are due to thermal generation at low electric fields and Poole–Frenkel accompanied by thermionic filed emission at high electric fields. The leakage current is correlated with the traps present in the polysilicon bulk and at the gate oxide/polysilicon interface which are estimated from the on-state current activation energy data. Analysis of the leakage current noise spectral density confirms that deep levels with uniform energy distribution in the silicon band gap are the main factors in determining the leakage current. The density of deep levels determined from noise analysis is in agreement with the value obtained from conductance acti...