Dimitrios Velenis

Reduced Delay Uncertainty in High Performance Clock Distribution Networks

The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A polynomial time algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay to the most critical data paths. Strategies for enhancing the physical layout of the clock tree to decrease delay uncertainty are also presented. Application of the methodology on benchmark circuits demonstrates clock tree topologies with decreased delay uncertainties of up to 90%. Techniques to enhance a clock tree layout have been applied on a set of benchmark circuits, yielding a reduction in delay uncertainty of up to 48%.

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty

The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented.

Buffer sizing for delay uncertainty induced by process variations

Controlling the delay of a signal in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high performance synchronous circuits. The effects of device parameter variations on the signal propagation delay of a CMOS buffer are described in this paper. It is shown that delay uncertainty is introduced due to variations in the current flow through a buffer. In addition, the variations in the parasitic resistance and capacitance of an interconnect line also affect the buffer delay. A design methodology that reduces the delay uncertainty of signals propagating along buffer-driven interconnect lines is presented. The proposed methodology increases the current flow sourced by a buffer to reduce the sensitivity of the delay on device and interconnect parameter variations.

Effects of parameter variations and crosstalk on H-tree clock distribution networks

Controlling the delay and the transition time of the clock signal in the presence of various noise sources, process parameter variations and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular, the effects of variations in power supply (VDD), temperature, and gate oxide thickness (tOX) on the clock signal delay and transition time are evaluated. In addition to parameter variations, crosstalk effects among the H-tree structure and other interconnect wires are investigated. It is shown that the delay and transition time of the clock signal is spatially dependent on interconnect crosstalk along an H-tree

Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees

Scaling of the on-chip feature size down into the deep submicron range has emphasized the importance of interconnect delay variations due to capacitive coupling. A methodology for reducing crosstalk noise on tree-structured interconnects is proposed in this paper. An algorithm is implemented to compute the optimal sequence of shielding insertion along a capacitively coupled interconnect tree. The reduction in crosstalk is verified through simulation and compared to alternative shielding schemes, considering the availability of limited shielding resources. It is demonstrated that the reduction in interconnect delay variations achieved by the proposed methodology is consistently higher. Furthermore, it is shown that delay variations between two critical nodes in a tree can also be reduced by the same shielding insertion approach

Effects of parameter variations and crosstalk noise on H-tree clock distribution networks

The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage (VDD), and temperature on the delay and the transition time of the clock signal are evaluated. Furthermore, the effects of crosstalk between an H-tree structure and other interconnect wires are investigated. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the clock signal are demonstrated

Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling

A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a non-zero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays by replacing clock buffers from predesigned cell libraries. Timing margin improvements of up to 18% are achieved through the application of non-zero clock skew scheduling in certain functional blocks of an industrial high performance microprocessor.

Power supply variation effects on timing characteristics of clocked registers

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the timing characteristics of registers are investigated in this paper. The sensitivity of the setup time and data propagation delay to power supply variations is demonstrated for four different register designs. Design modifications are proposed in order to enhance the robustness of each register design under VDD variations

Effects of process and environmental variations on timing characteristics of clocked registers

Violations of the timing constraints in a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling

A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated in this paper. It is shown that nonzero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a nonzero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays. Furthermore, a technique that significantly reduces the power dissipated in the noncritical data paths is demonstrated. The application of this technique combined with nonzero clock skew scheduling to the slower data paths is also described. Speed improvements of up to 18% and power savings greater than 80% are achieved in certain functional blocks of an industrial high performance microprocessor.