Ivan S. Kourtev

Timing Optimization Through Clock Skew Scheduling

This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.

Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking

Resonant clocking technologies are next-generation clocking technologies that provide low or controllable-skew, low-jitter and multi-gigahertz frequency clock signals with low power consumption. This paper describes a collection of circuit partitioning, placement and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with the resonant rotary clocking technology. Resonant rotary clocking technology inherently supports (and requires) non-zero clock skew operation, which permits further improved circuit performances. The proposed physical design flow entails integrated circuit partitioning and placement methodologies that permit the hierarchical application of non-zero clock skew system timing. This design flow is shown to be a computationally efficient implementation method.

A 64-way VLIW/SIMD FPGA architecture and design flow

Current FPGA architectures are heterogeneous, containing tens of thousands of logic elements and hundreds of embedded multipliers and memory units. However, efficiently utilizing these resources requires hardware designers and complex computer aided design tools. The paper describes several multi-processor architectures implemented on an FPGA, including a 64-way single interface multiple data (SIMD) and a variable size very long instruction word (VLIW) architecture. The design and synthesis of the target architectures are presented and compared for scalability and achieving parallelism. The performance and chip utilization of a shared register file is examined for different numbers of VLIW processing elements. The associated compilation flow is described based on the Trimaran VLIW compiler which achieves explicitly parallel instructions from C code. Benchmarks from the Media-Bench suite are being used to test the performance of the parallelism of both the software and hardware components.

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.

Reduced dynamic swing domino logic

A new reduced-swing domino logic technique is presented which provides significantly lower power dissipation as compared to traditional domino circuit structures. Additionally, the noise margins of the new circuit offer an improvement over standard domino design. The key idea of the new design style is to limit both the upper and lower bounds of the voltage swing at the internal dynamic node. The voltage swing at the inputs and the outputs of the domino circuit remains full-swing. A number of circuits are presented all of which have been designed and simulated in 0.18 micron technology. Analysis of simulation results show the potential for a 25-40% decrease in power consumption with an increased tolerance to noise. These improvements come at the expense of increased propagation delay and circuit area; the magnitude of which varies with the proposed circuit structures.

Simultaneous clock scheduling and buffered clock tree synthesis

This paper considers the problem of designing the topology of a clock distribution network in a synchronous digital system so as to enforce nonzero clock skew. A methodology and related algorithm for synthesizing the topology of the clock distribution network from a clock skew schedule derived from the circuit timing information is presented. The application of the algorithm to benchmark circuits shows that improvements of the minimum clock period ranging up to 64% can be achieved. These improvements are attained by exploiting non-zero clock skew throughout the synchronous system. Mathematically the problem of designing the clock distribution network is formulated as an integer linear programming problem which is efficiently solvable. The algorithm for synthesizing a clock tree is demonstrated on an example circuit.

Noise immunity of digital circuits in mixed-signal smart power systems

Experimental data describing circuit and physical design issues that influence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry affects digital latches. The experimental data characterize a variety of different noise mitigation techniques for the particular process technology circuit structures, signal/clocking interdependencies, and related conditions.

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling

A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated in this paper. It is shown that nonzero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a nonzero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays. Furthermore, a technique that significantly reduces the power dissipated in the noncritical data paths is demonstrated. The application of this technique combined with nonzero clock skew scheduling to the slower data paths is also described. Speed improvements of up to 18% and power savings greater than 80% are achieved in certain functional blocks of an industrial high performance microprocessor.

Efficient CAD development for emerging technologies using Objective-C and Cocoa

Future nanotechnologies will permit the manufacturing of computational systems of unprecedented complexity. It is not unreasonable to anticipate that, in order to analyze and design such systems, engineers will rely heavily on computer-aided design (CAD) software tools. As is the case with semiconductor CAD tools, the better one understands the underlying data structures and algorithms of a CAD tool, the more productive the user of the CAD tool is. The increasing challenges of future nanosystems will likely lead to blurring the division between system designers and the CAD designers and to merging of these two disciplines. Novel software development environments permitting powerful development of high-quality software will be required. This paper describes the experience of the authors with one such development framework based on the Objective-C programming language and the Cocoa application programming environment in a UNIX-based environment. These development choices were made because of the available programmer support, permitting development of complex applications in a straightforward way. A CAD application of moderate complexity for the simulation of asynchronous cellular arrays was developed with minimal effort. The authors believe that the ease of development using Cocoa is greater than in other similar development environments.

Performance metrics for asynchronous digital circuits applicable to computer-aided design

Computer-aided design (CAD) circuit techniques for synchronous circuits generally improve the quality of a circuit based on previously specified performance metrics such as cycle-time, latency and throughput (often expressed in terms of the clock period). Limited techniques to minimize worst-case delays and physical area of asynchronous circuits have been developed. Optimization algorithms for these circuits must recognize their average-case speed and control performance by using quantifiable metric specification to asynchronous circuits. The types of asynchronous circuits and the factors affecting their performance are surveyed in this paper. Techniques to compute and optimize the cycle-time, latency and throughput are analyzed to determine what these terms mean in the context of asynchronous circuits and the performance analysis of these circuits.