Kevin T. Tang

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.

Interconnect coupling noise in CMOS VLSI circuits

AbstmctInterconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or lass than the time of flight delay of the signal through the low resistivity interconnect. In this paper, closed form expressions for the coupling noise between adjacent interconnect are presented to estimate the coupling noise voltage on a quiet line. These expressions are based on an assumption that the interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should preferably be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.

Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections

Abstract The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive–capacitive interconnect lines is presented in this paper for different signal combinations. Analytical expressions characterizing the output voltage and the propagation delay of a CMOS logic gate are presented for a variety of signal activity conditions. The uncertainty of the effective load capacitance on the propagation delay due to the signal activity is also addressed. It is demonstrated that the effective load capacitance of a CMOS logic gate depends upon the intrinsic load capacitance, the coupling capacitance, the signal activity, and the size of the CMOS logic gates within a capacitively coupled system. Some design strategies are also suggested to reduce the peak noise voltage and the propagation delay caused by the interconnect coupling capacitance.

Delay and power expressions characterizing a CMOS inverter driving an RLC load

On-chip parasitic inductance has become an important design issue in high speed integrated circuits. On-chip inductance may degrade on-chip signal quality, affect transmission delay, and cause additional short-circuit power dissipation. The effects of on-chip inductance on the output voltage, propagation delay, and short-circuit power of a CMOS inverter are presented in this paper. Analytic equations characterizing the output voltage are derived based on an assumption of a fast ramp input signal. Closed form expressions describing the short-circuit power are also presented, The accuracy of these analytic equations is within 10% as compared to SPICE simulations. It is demonstrated that large inductive loads and fast input transition times can increase short-circuit current.

On-chip /spl Delta/I noise in the power distribution networks of high speed CMOS integrated circuits

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped RLC model. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak simultaneous switching noise voltage on the circuit behavior.

Peak crosstalk noise estimation in CMOS VLSI circuits

Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of flight delay of the signal through the interconnect. In this paper, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver is modeled as a capacitor. A closed form expression for the coupling noise between adjacent interconnect is presented to estimate the coupling noise voltage on a quiet line based on the assumption that these interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.

Delay uncertainty due to on-chip simultaneous switching noise in high performance CMOS integrated circuits

On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution networks, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous CMOS integrated circuits. Analytical expressions characterizing the on-chip simultaneous switching noise voltage and the output voltage waveform of a CMOS logic gate driving both a capacitive and a resistive-capacitive load are presented. The waveform of the output voltage signal based on the analytical expressions is quite close to SPICE. The estimated propagation delay is within 5% as compared to SPICE while the average improvement in accuracy can reach 10% as compared to a delay estimated without considering on-chip simultaneous switching noise. The analytical expressions presented provide an accurate timing model for non-negligible on-chip simultaneous switching noise in high speed synchronous CMOS integrated circuits.

Lumped versus distributed RC and RLC interconnect impedances

A Fourier analysis of on-chip signals in CMOS integrated circuits is presented in this paper. It is demonstrated that on-chip signals can be approximated by a Fourier series up to the 15th harmonic component. The effective load impedance characterizing a distributed RC and RLC line driven by a CMOS logic gate is based on a Fourier analysis of the on-chip signals. The voltage waveform based on the effective load impedance approaches a distributed RC and RLC line approximated by sections of lumped RC and RLC elements.

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. These transient IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of these transient IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient IR voltage drops can exceed 20% for a 20 Ω power line.

Transient analysis of a CMOS inverter driving resistive interconnect

Expressions characterizing the output voltage and propagation delay of a CMOS inverter driving a resistive-capacitive interconnect are presented in this paper. The MOS transistors are characterized by the nth power law model. In order to emphasize the nonlinear behavior of a CMOS inverter, the interconnect is modeled as a lumped RC load. The propagation delay of a CMOS inverter is characterized for both a fast ramp and a slow ramp input signal. The waveform of the output voltage based on these analytic equations is quite close to SPICE assuming a fast ramp input signal. The accuracy of the propagation delay model for both fast ramp and slow ramp input signals is within 7% as compared to SPICE simulations.