Dimitris Bekiaris

A mixed style multiplier architecture for low dynamic and leakage power dissipation

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area and fast speed advantages of tree multipliers. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that while the bypass technique offers the minimum dynamic power consumption value, the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures. Furthermore, the tree part of the mixed architecture has enough timing slack to be implemented with high Vth low leakage components, offering an extra 20%–30% leakage power saving, which is a considerable value in deep submicron technologies.

Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic

This paper presents a new programmable finite-impulse response (FIR) digital filter scheme based on a low latency, power efficient architecture with reduced hardware complexity. In the proposed scheme, the input data is kept in bit-parallel form, while the coefficients enter the circuit in digit-serial form. The coefficient digits are encoded using the Modified Booth algorithm to reduce the partial products required for each multiplication. The structure of the filter is based on the technique of merging adjacent multiply-add units. The computation of the intermediate results is implemented using the carry-save arithmetic. Also, the coefficient digits of adjacent multiply-add units enter the filter in digit-skew form, while the input data sample remains stable until the relative output sample is produced. Thus, the proposed architecture results in a circuit with reduced hardware cost and lower power consumption, compared to other schemes presented in the bibliography.

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.

Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow

Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfigurable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the data path of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi Vth components, for the design of low-power morphable multipliers. Experimentation with these multipliers in a high-level synthesis flow show that they can offer performance, area and power improvements compared to alternative architectures, making them valuable building blocks for hardware synthesis.

A mixed style architecture for low power multipliers based on a bypass technique

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption. While this idea offers great savings mainly to array multipliers, due to their regular interconnection scheme, the reduced area and fast speed of tree multipliers is a real temptation for the designer. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that the bypass technique offers minimum power consumption for all cases while the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures.

A standard-cell library suite for deep-deep sub-micron CMOS technologies

The continuous scaling of CMOS transistor and interconnect geometries brings to light novel challenges regarding the design of VLSI systems in the nanoscale era. On the other hand, most of the forthcoming deep-deep submicron technologies are not yet mature to be used for fabrication. Hence, the development of standard-cell libraries at the nanometer regime is emerging, in order to estimate the behavior of complex systems in short-term technology nodes. In this paper, we introduce a standard-cell library generator flow for sub-65nm nodes, based on scaling rules presented in the literature. Our goal is to create a set of complete standard cell libraries enabling the design of large digital systems in technologies not yet available for fabrication. The generated libraries are compatible with the state-of-the-art industrial tool flows and they have been evaluated by benchmarks of medium and large complexity.

The MOSART Mapping Optimization for Multi-Core ARchiTectures

MOSART project addresses two main challenges of prevailing architectures: (1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; (2) The difficulties in programming heterogeneous, multi-core platforms MOSART aims to overcome these through a multi-core architecture with distributed memory organization, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: (1) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

A temperature-aware time-dependent dielectric breakdown analysis framework

The shrinking of interconnect width and thickness, due to technology scaling, along with the integration of low-k dielectrics, reveal novel reliability wear-out mechanisms, progressively affecting the performance of complex systems. These phenomena progressively deteriorate the electrical characteristics and therefore the delay of interconnects, leading to violations in timing-critical paths. This work estimates the timing impact of Time-Dependent Dielectric Breakdown (TDDB) between wires of the same layer, considering temperature variations. The proposed framework is evaluated on a Leon3 MP-SoC design, implemented at a 45nm CMOS technology. The results evaluate the systems performance drift due to TDDB, considering different physical implementation scenarios.

SYSTEMATIC DESIGN AND EVALUATION OF RECONFIGURABLE ARITHMETIC COMPONENTS IN THE DEEP SUBMICRON DOMAIN

In the era of deep submicron integration, digital design complexity is increasing with rates that are hard to follow. On one hand, market demand for newer, faster and reliable applications never st...

Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments

Modern digital design has been greatly forced to offer More-Moore integration densities and very high operation frequencies for demanding applications. In this search-for-performance race, alternative and less radical More-than-Moore solutions are emerging, like reconfigurable computing. Reconfigurable computing stands between hardware and software and promises to offer the formers performance alongside with the latters flexibility. Research in the field deals with fine or coarse grain reconfigurable components and efficient ways to map applications onto them. In this paper, a systematic design methodology and evaluation of a coarse grain reconfigurable component targeting the ASIC domain is presented. The specific component is a morphable architecture, that works in mutually exclusive modes, offering different functionality in each mode. The novelty presented in this paper is a systematic evaluation of the scalability of the morphable component. Continuously functionally improved modes are evaluated for performance, area and power, in order to choose the best architecture for a number of widely used DSP applications. Overall, a power* performance improvement of up to 24% is reported and a power* area of up to 13% compared to conventional, non-reconfigurable component architectures.