Dinesh Pamunuwa

Maximizing throughput over parallel wire structures in the deep submicrometer regime

In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing throughput over a given metal area. This analysis is used to show that there is a clear optimum configuration for the wires which maximizes the total bandwidth. Additionally, closed form equations are derived, the roots of which give close to optimal solutions. It is shown that for wide buses, the optimal wire width and spacing are independent of the total width of the bus, allowing easy optimization of on-chip buses. Our analysis and results are valid for lossy interconnects as are typical of wires in submicron technologies.

Repeater insertion to minimise delay in coupled interconnects

Signalling over long interconnect is a dominant issue in electronic chip design in current technologies, with the device sizes getting smaller and smaller and the circuits becoming ever larger. Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnect. In deep sub-micron technologies, as the wires are spaced closer and closer together and signal rise and fall times go into the sub-nano second region, the coupling between interconnects assumes great significance. The resulting crosstalk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. In this paper we attempt to quantify the effect of worst-case capacitive crosstalk in parallel buses and look at how it affects repeater insertion in particular. We develop analytic expressions for the delay, buffer size and number that are suitable in a-priori timing analyses and signal integrity estimations. All equations are checked against a dynamic circuit simulator (SPECTRE).

Modelling NEM relays for digital circuit applications

A reduced-order model for NEM relays is presented that combines electro-mechanical beam actuation and landing of beam tip on the surface electrode. This model shows a deviation of less than 2%, for the DC as well as the transient response for beam actuation in a circuit simulation, when compared to a finite-element simulation. It also shows an excellent match for the energy. The model allows accurate circuit simulation to aid in NEM-relay based logic design, and facilitates the quantification of key gate-level metrics.

A global wire planning scheme for Network-on-Chip

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.

Analytical Compact Model in Verilog-A for Electrostatically Actuated Ohmic Switches

Nowadays, electronics face a challenge regarding the power consumption of integrated circuits (ICs). There is a need for new devices that can provide improved switching capabilities. The downscaled electrostatically actuated ohmic switch, as a (re)emerging device, is a promising candidate to meet this need. To bring such a device seamlessly into IC design, it must be accompanied by an accurate, fast and robust analytical compact model. The development and the main characteristics of such a model are described within this paper. Extensive numerical simulations and measurements have been used to validate the model.

Energy and Latency Optimization in NEM Relay-Based Digital Circuits

Digital circuits based on nanoelectromechanical (NEM) relays hold out the potential of providing an energy efficiency unachievable by conventional CMOS technology. This paper presents a detailed analysis of the operating characteristics of fabricated curved cantilever NEM relays using a comprehensive physical model. The mode of energy distribution within the electrical and mechanical operational domains of the relay is described in detail and the energy saving achievable by the technique of body-biasing is quantified. The analysis further reveals that the latency in a relay can be much larger or much smaller than the nominal mechanical delay depending on the point of actuation in the oscillation of the beam that takes place after pull-out. The methods that can utilize this phenomenon to reduce the latency of relay-based circuits are discussed, thus addressing one of the biggest challenges in NEM relay-based design.

On dynamic delay and repeater insertion in distributed capacitively coupled interconnects

Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnects. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nanosecond region, increased crosstalk has implications for the data throughput and signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).

Optimising bandwidth over deep sub-micron interconnect

In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies.

Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-resistance patterns

Active gate driving provides an opportunity to reduce EMI in power electronic circuits. Whilst it has been demonstrated for MOS-gated silicon power semiconductor devices, reported advanced gate driving in wide-bandgap devices has been limited to a single impedance change during the device switching transitions. For the first time, this paper shows multi-point gate signal profiling at the sub-ns resolution required for GaN devices. A high-speed, programmable active gate driver is implemented with an integrated high-speed memory and output stage to realise arbitrary gate pull-up and pulldown resistance profiles. The nominal resistance range is 120 μΩ to 64 Ω, and the timing resolution of impedance changes is 150 ps. This driver is used in a 1 MHz GaN bridge leg that represents a synchronous buck converter. It is demonstrated that the gate voltage profile can be manipulated aggressively in nanosecond scale. It is observed that by profiling the first 5 ns of the control devices gate voltage transient, a reduction in switch-node voltage oscillations is observed, resulting in an 8–16 dB reduction in spectral power between 400 MHz and 1.8 GHz. This occurs without an increase in switching loss. A small increase in spectral power is seen below 320 MHz. As a baseline for comparison, the GaN bridge leg is operated with a fixed gate drive strength. It is concluded that p-type gate GaN HFETs are actively controllable, and that EMI can be reduced without increasing switching loss.

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns

This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.