Roshan Weerasekera

Interconnect design and analysis for Through Silicon Interposers (TSIs)

The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due to the increased power density, higher I/O count, interconnect bandwidth, and timing closure requirements. Silicon carrier with Through Silicon Vias (TSVs) or TSI technology is identified as a system and packaging level solution to overcome all those challenges. In this paper we describe the key electrical elements in a typical TSI digital system and discuss their impact on overall system performance. We also discuss the system level power integrity analysis for TSI as its power delivery is one of the major engineering challenges.

On the Impact of Through-Silicon-Via-Induced Stress on 65-nm CMOS Devices

Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm, respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between -55°C and 125 °C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

Heterogeneous 2.5D integration on through silicon interposer

Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity (<1 mm separation) compared with several centim...

High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer

In this paper, two high-speed and low-power I/O circuits are developed using through-silicon-interposer (TSI) for 2.5D integration of multi-core processor and memory in 65 nm CMOS process. For a 3 mm TSI interconnection of transmission line (T-line), the first I/O circuit is a low-voltage-differential-signal (LVDS) buffer and the second one is a current-mode-logic (CML) buffer. To compensate the high-frequency loss from T-line, a pre-emphasis circuit is deployed in the LVDS buffer, and a wide-band inductor-matching is deployed in the CML buffer. Based on the post layout simulation results, the LVDS buffer can achieve 360 mV peak-to-peak differential output signal swing and 563 fs cycle-to-cycle jitter with 10 Gb/s bandwidth and 4.8 mW power consumption. The CML buffer can achieve 240 mV peak-to-peak differential output signal swing and 453 fs jitter with 12.8 Gb/s data-rate and 1.6 mA current consumption under 0.6 V ultra low-power supply.

Through-Silicon Interposer (TSI) co-design optimization for high performance systems

Driven by the internet bandwidth ever increasing demand, modern logic integrated circuits (IC) need to cope for logic to memory (DRAM) data throughput above the Terabit per seconds (Tbps) range [1]. Such logic to DRAM interface is affected by the memory wall bottlenecks like: logic operating at much higher throughput and lower latency than DRAM individual modules, and with limited pin count capability organic packaging solutions leading to system architecture using serialization techniques (at the expense of power dissipation and additional circuit latency). Those bottlenecks cannot be addressed individually and need a more global approach with new packaging solutions, new devices and overall enhanced architecture. We will present in this study a silicon packaging solution that can be optimized to achieve the highest possible throughput between logic and DRAM. First, we will explain the concept of high performance silicon carrier with its key specifications as well as the metrics to be analyzed, and then we will provide design rules guidelines and a methodology to optimize such silicon carrier for the highest possible throughput performance.

An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate

Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs.

CMOS based high density micro array platform for electrochemical detection and enumeration of cells

A highly sensitive label-free complementary-metal-oxide-semiconductor (CMOS) based high density micro-array for electrochemical detection and enumeration of breast tumor cell (MCF-7) is presented. The electrochemical impedance spectroscopy (EIS) based detection platform exhibited detection at single cell resolution (22 μm) and enumeration with mapping accuracy of ~80%. Maximum tumor-cell impedance increase of 28% was recorded.

Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

Two-and-a-half-dimensional integration enables high-density interdie connections with low cost. This paper presents a through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration.

Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar

Non-volatile memory (NVM) is one recent promising solution to build the next generation of memory system. Compared to other non-volatile devices such as flash, phase-change random-access-memory (PCRAM), memristor and etc., the emerging conductive-bridge random-access-memory (CBRAM) has shown advantages in accessing speed, power and endurance. In this paper, design of 3D-stacked NVM is explored with the use of CBRAM-crossbar. Specifically, accurate performance modeling of CBRAM-crossbar structure is studied within the corresponding design platform developed at device and system levels. Experiments show that, compared to PCRAM, the proposed CBRAM-crossbar based memory achieves 10x~100x faster accessing time, at least 100x less operation power, and 100x longer endurance.

Analysis of signal integrity(SI) robustness in through-silicon interposer (TSI) interconnects

This paper describes the electrical characteristics of the fine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB system from low data rates to higher data rates. Our case-study shows that even though highly resistive wires are used in silicon carrier the interconnects are SI robust due to the shorter die to die interconnect length and the absence of package parasitics.