Ding-Yun Chen

A novel parallel H.264 decoder using dynamic load balance on dual core embedded system

The dual-core environment is more and more popular in embedded system recently. The limited buffer and limited bandwidth are critical for parallel algorithm in embedded system. This paper proposes a novel parallel algorithm using functional partitioning with dynamic load balance for video decoder. The video decoding flow of each macroblock is dynamically separated for different cores according to the buffer queue level. The extra intercommunication buffer size requires only 1.6% buffer size of traditional data partitioning algorithm for 720p decoder. The speed-up ratio is 1.74 times in average compared to original single thread code. The experiment result shows the proposed algorithm can real-time decode H.264 720p high profile on ARM Cortex-A9 400MHz dual-core system.

A panoramic video system by direct manipulation video navigation

This paper presents a panoramic video system by direct manipulation video navigation without any image stitching. Our panoramic video browsing is interacted with user by displaying overlapped region of consecutive input video frames with corresponding viewing angle. That is, when user slides, the panoramic video will switch video frames to corresponding viewing angle according to sliding distance. When user stops to slide, the video will display the overlapped region of consecutive video frames in the same viewing angle. The switching of viewing angle and cropping of the overlapped region are based on video frame registration. The major advantage of our method is to provide a panoramic video navigation from hand-held mobile camera phone with low computation and high quality. Comparing to other panoramic video stitching approaches, our method can guarantee no ghosting and no distortion. Our demo video is in http://youtu.be/XYpPAdypIuI for detail.

MVSE: A Multi-core Video decoder System level analytics Engine

Multi-core platform has become a trend in hand-held embedded systems, such as smartphone and tablet. To improve the video decoding performance by using the multiple cores, one of parallel algorithms should be adopted. However, different parallel algorithm should be selected for different video standard on different platform. Therefore, an engine to estimate performance on a target platform from existing single-thread video decoder is very helpful. This paper proposes a Multi-core Video decoder System level analytics Engine (MVSE) to estimate the performance on a target multi-core platform. In the MVSE, a general video decoder runs according to profiling data and macroblock information by three major parallel algorithms. The profiling data and macroblock information are obtained from existing single-thread video decoder so that the MVSE can support different video standard. The MVSE runs on target platform to consider the effect of memory access contention and cache intercommunication, which are traditionally difficult to estimate. Our experimental result shows the MVSE estimation is accuracy enough. The estimation results from MVSE shows the best speedup ratio is 1.7 times in a dual-core platform and 2.9 times in a quad-core platform for H.264 720p decoding. In addition, MVSE is also helpful for hardware and software co-design in heterogeneous computing. The experimental results show the best performance is improved by VLD hardware, and the speedup ratio is 2.3 times in a dual-core platform and 3.9 times in a quad-core platform.