Chung-Hung Tsai

A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

A first-reported 4K×2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted memory management unit (W-MMU) and multi-standard architecture reduce DRAM bandwidth and cost by 43% and 28%, respectively. This 4K Main-10 HEVC video decoder chip integrates 3.4M gate counts with area of 2.86mm2. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [6] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback for UHD-TV applications.

A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver

A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.

A panoramic video system by direct manipulation video navigation

This paper presents a panoramic video system by direct manipulation video navigation without any image stitching. Our panoramic video browsing is interacted with user by displaying overlapped region of consecutive input video frames with corresponding viewing angle. That is, when user slides, the panoramic video will switch video frames to corresponding viewing angle according to sliding distance. When user stops to slide, the video will display the overlapped region of consecutive video frames in the same viewing angle. The switching of viewing angle and cropping of the overlapped region are based on video frame registration. The major advantage of our method is to provide a panoramic video navigation from hand-held mobile camera phone with low computation and high quality. Comparing to other panoramic video stitching approaches, our method can guarantee no ghosting and no distortion. Our demo video is in http://youtu.be/XYpPAdypIuI for detail.

MVSE: A Multi-core Video decoder System level analytics Engine

Multi-core platform has become a trend in hand-held embedded systems, such as smartphone and tablet. To improve the video decoding performance by using the multiple cores, one of parallel algorithms should be adopted. However, different parallel algorithm should be selected for different video standard on different platform. Therefore, an engine to estimate performance on a target platform from existing single-thread video decoder is very helpful. This paper proposes a Multi-core Video decoder System level analytics Engine (MVSE) to estimate the performance on a target multi-core platform. In the MVSE, a general video decoder runs according to profiling data and macroblock information by three major parallel algorithms. The profiling data and macroblock information are obtained from existing single-thread video decoder so that the MVSE can support different video standard. The MVSE runs on target platform to consider the effect of memory access contention and cache intercommunication, which are traditionally difficult to estimate. Our experimental result shows the MVSE estimation is accuracy enough. The estimation results from MVSE shows the best speedup ratio is 1.7 times in a dual-core platform and 2.9 times in a quad-core platform for H.264 720p decoding. In addition, MVSE is also helpful for hardware and software co-design in heterogeneous computing. The experimental results show the best performance is improved by VLD hardware, and the speedup ratio is 2.3 times in a dual-core platform and 3.9 times in a quad-core platform.

A 363-µW/fps power-aware green multimedia processor for mobile applications

In this paper, a power-aware and low power multimedia processor is presented. A novel clock gating scheme and dynamic frequency selection (DFS) are implemented to minimize the power dissipation and it integrates 7-standards (H.264 / VC1 / RV / AVS / MPEG-1 / MPEG-2 / MPEG-4) with several resource-sharing techniques in both algorithmic and architectural levels so as to achieve significant area and power reduction. In this work, our proposal also adopts several fine-grain power scalability (FGPS) technologies which can reduce a noticeable power consumption. The processor supports a wide range of decoding resolution ranging from CIF to full-HD under the 20~288MHz of working frequency and 60fps of frame rate with 363 μW/fps of power dissipation at 1.2V supply voltage and fabricated using 40nm 1P7M CMOS process with core area 1.40 mm2.

A 775-µW/fps/view H.264/MVC decoder chip compliant with 3D Blu-ray specifications

A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a single die. Moreover, it features pipeline management and clock management units so as to improve the processing throughput and clock power efficiency. A test chip for not only single-view video but multi-view H.264/MVC decoding has been designed and fabricated using 40nm 1P7M CMOS process with core area 1.22mm2. Core power dissipation is about 46.5mW under 1920×1080 resolution of single view 60fps or stereo-view 30fps.

Area and Memory Efficient Architectures for 3D Blu-ray-compliant Multimedia Processors

A 3D Blu-ray-compliant multimedia processor integrating video decoder, display and graphic engines is presented. To cope with the bandwidth/cost-starved Blu-ray system, this design exploits the time-sharing techniques, leading to 31.3% and 29.1% of area reduction in display and decoder parts. Moreover, a graphic and on-screen-display hardwired handshake effectively reduces the DRAM space by 40%. A smart graphic command removal eliminates the redundant memory accesses by 14%. For 3D Blu-ray playback requirements, stereo full-HD video decoding, 24Hz display, and stereoscopic graphic UI are realized under the frequency of 333MHz, 148MHz, and 333MHz, respectively. This test chip is fabricated in 40nm CMOS process with core area of 3.92mm2 and power dissipation of 124.1mW.

A 1.94mm 2 , 38.17mW dual VP8/H.264 Full-HD encoder/decoder LSI for Social Network Services (SNS) over smart-phones

A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of webs video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm2 of core area. Several area-efficient techniques are realized, leading to 43.6% of area reduction. A new rate control is designed to facilitate the adaptation of video data and frame rates for network services. Two fast algorithms and new bool encoder/decoder are proposed to enhance power efficiency. This chip consumes 28.15mW and 10.02mW of VP8 encoder and decoder average power for 1080p@30fps at 0.9V, respectively.