Dinis M. Santos

A novel high gain, high bandwidth CMOS differential front-end for wireless optical systems

This paper describes a high performance CMOS differential input front-end, designed for optical wireless communications. The front-end achieves a 50 MHz bandwidth and a 400 k/spl Omega/ transimpedance gain (20 THz/spl Omega/ gain-bandwidth product) with the targeted input photodiode junction capacitance of 10 pF. The input dynamic range is 60 dB, obtained through a switched step gain approach, and the input referred noise is under 8.2 pA//spl radic/Hz. An integrated circuit has been produced using a double poly, double metal, 0.8 /spl mu/m CMOS technology.

Oscillatorless clock multiplication

This paper presents a technique for clock multiplication without local oscillators. This technique uses a DLL, thus presenting lower jitter than traditional PLL-based oscillator systems. Furthermore, it provides directly 50% duty-cycle clocks. This method is implemented both in a programmable custom circuit able to perform clock multiplication with integer factors from 2 to 8, and in a simpler hybrid system. Both simulations in the full-custom design and experimental results in the hybrid system support our proposal.

Site evaluation and RFI spectrum measurements in Portugal at the frequency range 0.408–10 GHz for a GEM polarized galactic radio emission experiment

Abstract We probed for radio frequency interference (RFI) at three potential galactic emission mapping experiment (GEM) sites in Portugal using custom made omnidirectional disconic antennas and directional pyramidal horn antennas. For the installation of a 10-m dish dedicated to the mapping of polarized galactic emission foreground planned for 2005–2007 in the 5–10xa0GHz band, the three sites chosen as suitable to host the antenna were surveyed for local radio pollution in the frequency range 0.01–10xa0GHz. Tests were done to look for radio broadcasting and mobile phone emission lines in the radio spectrum. The results show one of the sites to be almost entirely RFI clean and showing good conditions to host the experiment.

Clock Distribution Strategy for IP-based Development

This paper presents a high-level clock distribution strategy for usage in a design-and-reuse environment. This strategy allows for controlled clock distribution across an arbitrary number of blocks through the usage of controlled delay lines. A new clock frequency multiplication structure optimised for this clock distribution strategy is finally proposed, since multifrequency clock support is highly desired.

Bandwidth Aspects in Second Generation Current Conveyors

This paper discusses bandwidth problems associated with second-generation current conveyors (CCII). In particular, our work is centered in high-capacitance applications, and has been oriented for wireless optical links and applied physics. We discuss techniques for improving bandwidth in these CCIIs, and develop a new CCII structure with larger bandwidth than traditional circuits. These circuits are then compared in terms of their noise and dynamic range characteristics. A test circuit was developed to verify these different bandwidth behaviors.

A 0.8-/spl mu/m CMOS, 622 Mb/s SDH/SONET communication system

This paper describes a 0.8 /spl mu/m CMOS communication system designed for 622 Mb/s SDH/SONET links. The single-chip system implements all line interface functions needed by the link. The emitter performs parallel bus interface, parallel-to-serial conversion and optional scrambling for line testing. An output buffer to attack the laser driver is also included. The receiver performs post-amplification, clock recovery, frame detection and optional descrambling, followed by serial-to-parallel conversion and parallel bus interface.

A 0.7 /spl mu/m CMOS clock recovery circuit for 622 Mb/s SDH systems

A clock recovery circuit for SDH STM-4 applications is described. The circuit has been implemented in a 0.7 /spl mu/m CMOS technology. A digital VCO has been designed for the 622 MHz frequency. The chip sustained working frequencies from 550 up to 700 MHz. The recovered clock jitter (peak-to-peak) is under 150 ps, for SDH STM-4 data signals.

A reverse GPS architecture for tracking and location of small objects

A novel architecture for the location and tracking of small objects using a GPS-like architecture is described. Unlike the conventional GPS system, the proposed architecture places the emitters at the objects to be tracked and the receivers at fixed (earth) stations, so that the emitters can be made very simple and most of the intelligence of the system is located at the receivers. Due to the very low signal-to-noise ratio of the received signals, signal recovery techniques based on correlation and codification, similar to the ones used in spread-spectrum systems, are used in this architecture. The expected noise budget and coding techniques to be used are discussed.

Highly efficient multi-point clock distribution networks

This paper presents techniques for top-level high-speed clock distribution in large VLSI circuits. The techniques described resort to feedback mechanisms on the clock path, using controlled delay lines. These techniques allow the synchronization of a large number of top-level domains without extra interconnection lines, with clear performance improvements over other proposals.

Simulation and modelling of digital delay locked loops

This paper discusses some results for simulation and modeling of charge-pump Delay Locked Loops (DLLs). A novel model based on a sampled-time approach is presented, and used for jitter analysis. The model is applied to input signal jitter, internally generated jitter and is further extended to handle jitter effects related with the control charge-pump. Behavior models for simulation purposes are derived from the theoretical model, and design considerations based on these are presented.