Dionysios Manessis

Printing Solder Paste in Dry Film - A Low Cost Fine-Pitch Bumping Technique

There is a steady trend to decrease bump pitch and the total cost for the bumping process. Several techniques for bumping are available such as screen printing of solder paste through metal stencils, electroplating of bumps, ball placement or C4NP. Initially there appears to be a number of choices for bumping, however after looking at the details the choices are significantly reduced. The use of ball placement or screen printing is limited to larger sized bumps and coarser pitches. Bumping by electroplating which is popular for fine-pitch bumping is restricted to single or double component systems. Electroplating of triple component systems like SnAgCu which are interesting for lead free bumping requires a very complex process monitoring. Additionally, electroplating of ternary metal systems is not yet suitable for manufacturing. In this paper the basic process steps for a different bumping technology are discussed in detail. This technology uses a solder paste which is printed into photo-structured dry film. Test wafers with Ni + flash-Au final metallisation were provided. A dry film photo resist was laminated onto the wafers, exposed and developed. Next, solder paste was printed into the structured resist. The wafers were then passed through a Pb-free reflow profile. After the reflow, the dry film was successfully stripped. A variation of pad size and resist openings were investigated. Correlation between design and results are discussed.

Innovative approaches for realisation of embedded chip packages - Technological challenges and achievements

Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturization by stacking multiple layers of embedded components. Among its merits, it provides superior electrical performance by short and geometrically well controlled interconnects as well as a homogeneous mechanical environment for the chips and thus resulting in superior reliability. At PCB manufacturing level, 50 µm thin chips have been embedded with pitches up to 200 µm in up to 18″×24″ panels. This paper shows the further developments in chip embedding technologies to incorporate chips with even smaller pitches. The technology developed in this study does not necessitate expensive redistribution layers for enlarging the pad pitch. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400µm pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100µm pitch. All Embedded chip-QFN packages have been manufactured in 10″×14″ panels at prototype level. This paper explains in detail all process steps and technical challenges encountered for the QFN package manufacturing. The final packaging routing necessitates challenging technology developments in ultra fine line patterning. The paper shows the successful employment of laser-direct-imaging technology in semi-additive-processes for the creation of very fine 18µm copper lines with 10µm spaces between them. Very thin 2µm Copper foils were used for this study as a plating base and for the final Copper flash etching during semi-additive-process. These important technological developments have been achieved with advancements in laser direct imaging technique of negative photoresist films which allows the whole patterning to be done without use of expensive masks. Additionally, it cuts off processing time and it can yield very dense copper patterning up to the technological limit of the LDI technique. The paper also elaborates on embedding strategies for chips with contact pitches even smaller than 100µm either with vialess methods to contact pads or by flip chip interconnection and then chip embedding. This study shows promising results for embedding of chips with different contact pitches through alternative embedding strategies and in conjunction with developments for very dense copper routing, it provides strong evidence for the manufacturability of highly miniaturised embedded chip system-in-packages.

Alternative UBM for Lead Free Solder Bumping using C4NP

This paper analyzes two alternative under bump metallurgy (UBM) structures: sputtered TiW/Ni and electroless Ni/immersion Au (ENIG), with and without Pd. Wafers were fabricated with these UBM structures, solder applied with C4NP, and chip level stressing performed to determine the robustness of these alternative stack-ups. Microelectronic packaging continues the migration from wire bond to flip chip first level interconnect (FLI) to meet aggressive requirements for improved electrical performance, reduced size and weight. Analysis of these structures following multiple reflows and thermal cycling is presented.

Development of an electro-optical circuit board technology with embedded single-mode glass waveguide layer

The goal of our research is the development of a single-mode electro-optical circuit board, the single-mode board-to-board pluggable connector and the single-mode chip-to-board coupling interface to silicon photonic devices. In this paper, the single-mode glass waveguide process is presented based on thermal silver ion-exchange for fabrication of low loss glass waveguide panels that will be developed for embedding as core layer of such printed circuit board. The single-mode glass waveguides (SM-WGs) were fabricated on 150 mm wafer size for characterization of different embedding scenarios. In the best case the measured propagation loss before and after lamination is below 0.1 dB/cm (λ=1550 nm). A suitable glass waveguide layer and embedding process was developed that can be applied for single-mode electro-optical circuit board fabrication.

Embedded power electronics for automotive applications

The automotive industry has a strong demand for highly reliable and cost-efficient electronics. Especially the upcoming generations of hybrid cars and fully electrical vehicles need compact and efficient 400 V power modules. Within the engine compartment installation space is of major concern. Therefore small size and high integration level of the modules are needed. Conventionally IGBTs and diodes are soldered to DCB (Direct Copper Bond) ceramics substrates and their top contacts are connected by heavy Al wire bonds. These ceramic modules are vacuum soldered to water-cooled base plates. Embedding of power switches, and controller into compact modules using PCB (Printed Circuit Board) technologies offers the potential to further improve the thermal management by double-sided cooling and to reduce the thickness of the module. In a German funded project named “HI-LEVEL” partners from industry and research are developing a next generation of automotive power modules with embedded components. The final goal is a 50 kW inverter for hybrid electrical cars. In the paper the ongoing development and realization of a 10 kW test vehicle is described.

Development of embedded power electronics modules

The use of Printed Circuit Board (PCB) technology for device packaging offers new opportunities to solve these challenges. During the past decade embedding of semiconductor chips into PCB structures evolved from a research topic to volume production. The paper will briefly describe this development and categorize todays embedding technologies. First modules with embedded chips are in production in Asia and Europe, mainly for mobile applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential. The automotive industry has a strong demand for highly reliable and cost-efficient electronics. Especially the upcoming generations of hybrid cars and fully electrical vehicles need compact and efficient 400 V power modules. Within the engine compartment installation space is of major concern. Therefore small size and high integration level of the modules are needed. Embedding of power switches, and controller into compact modules using PCB (Printed Circuit Board) technologies offers the potential to reduce the thickness and size of the module. In order to replace DCB ceramics, a structure of thermal laminate material between Cu layers has been developed and the capability for thermal conduction and electrical insulation has been evaluated. For the assembly of large power IGBTs with sizes of 100 mm² and larger, new silver sintering pastes have been evaluated. They enable a pressure-less sintering at 200 °C, compatible with PCB materials. To handle the high switching current of up to 200 A, suitable copper tracks in the PCB are required. The realization of such thick copper lines with thickness up to 1 mm requires advanced processing, compared to conventional multilayer PCB production. In order to form complex power systems out of modules with embedded chips interconnections by Ag sintering are under development.

Microtechnology For Realization Of Dielectrophoresis Enhanced Microwells For Biomedical Applications

Microtechnologies are widely used in many applications as e.g. for the automotive or telecommunication industry. But it could be also a versatile tool for biological and biomedical applications. Microwells have been established long in this application field but remained without any additional functionality up to now. Merging new fabrication techniques and handling concepts with microelectronics enables the realization of intelligent microwells suitable for future applications e.g. improved cancer treatment. For the implementation of a dielectrophoresis enhanced microwell device a technology based on standard PCB technology has been developed. But as materials from PCB technology are not biocompatible new materials have to be selected, tested and processes adapted to these new packaging materials. With promising preselected materials for an enhanced microwell device biocompatibility tests have been carried out. As base conducting metal layer aluminum has been selected. Different dielectric materials were evaluated with focus on their processability. Goal of this preselection study was to find materials, which allow a fine structuring and realization of thin layers for the required application geometries. Thin aluminum foils are structured by laser micro machining and laminated successively to obtain minimum registration tolerances of the respective layers. The microwells are also laser machined into the laminate, allowing capturing and handling individual cells within a dielectrophoretic cage realized by the structured aluminum as well as providing access holes for the layer-to-layer interconnection. Furthermore, surface treatments with e.g. thiols and fluorinated acrylates on different materials were inspected by surface tension and wetting analysis to allow designing the hydrophilic/hydrophobic microfluidic networks required for the microwell device. First demonstrators are presenting the developed technologies and structures realized. In summary this paper describes the material selection for a biocompatible microwell device, the development of the individual process steps and results on the microstructuring as well as on biocompatibility of the materials are given.

Formation and characterization of cobalt-reinforced Sn-3.5Ag solder

Solders under severe service environments should have enhanced mechanical properties. To achieve this goal, the approach of composite solder reinforced by second-phase particles was tried in this study. Cobalt (Co) and eutectic Sn-3.5Ag were selected as a reinforcing particle and solder matrix, respectively. Co particles and solder paste were mechanically mixed to make uniform mixing at Co weight fractions from 0.1 % to 2.0 %. For the Co-mixed Sn-3.5Ag solder pastes, melting temperature and spreading area were measured. The solder pastes were stencil printed on test substrates and reflowed to form solder bumps. Ball shear test was performed to examine shear strength of Co-reinforced Sn-3.5Ag solder bumps. As a result, small amount of Co addition did not alter melting temperature and spreadability. Maximum shear strength of Co-reinforced Sn-3.5Ag solder bumps showed 28 % increase compared to normal ones. The increase in shear strength was due to facetted needle-like (Cu,Co)3Sn2 intermetallic compounds (IMCs)

Design process supporting simulations on wafer level packages

The design process of innovative and advanced microelectronic systems requires the mechanical behaviour to be taken into account in order to achieve a high level of reliability from the very beginning of the electronic design. In this respect, all essential thermal and mechanical influences during manufacturing as well as operation need to be considered. The influence of design and process parameters on thermomechanical stresses is analysed numerically and pre-optimised for two different types of packages for wireless communication applications in the high frequency range. As a result, design and process improvements can be recommended for assembly levels 1 (wafer level) and 2 (interactions with the carrier and other components).

Electro-optical circuit board with single-mode glass waveguide optical interconnects

A glass optical waveguide process has been developed for fabrication of electro-optical circuit boards (EOCB). Very thin glass panels with planar integrated single-mode waveguides can be embedded as a core layer in printed circuit boards for high-speed board-level chip-to-chip and board-to-board optical interconnects over an optical backplane. Such singlemode EOCBs will be needed in upcoming high performance computers and data storage network environments in case single-mode operating silicon photonic ICs generate high-bandwidth signals [1]. The paper will describe some project results of the ongoing PhoxTroT project, in which a development of glass based single-mode on-board and board-to-board interconnection platform is successfully in progress. The optical design comprises a 500 μm thin glass panel (Schott D263Teco) with purely optical layers for single-mode glass waveguides. The board size is accommodated to the mask size limitations of the fabrication (200 mm wafer level process, being later transferred also to larger panel size). Our concept consists of directly assembling of silicon photonic ICs on cut-out areas in glass-based optical waveguide panels. A part of the electrical wiring is patterned by thin film technology directly on the glass wafer surface. A coupling element will be assembled on bottom side of the glass-based waveguide panel for 3D coupling between board-level glass waveguides and chip-level silicon waveguides. The laminate has a defined window for direct glass access for assembling of the photonic integrated circuit chip and optical coupling element. The paper describes the design, fabrication and characterization of glass-based electro-optical circuit board with format of (228 x 305) mm2.