Klaus Ruhmer

Advancements in fabrication of glass interposers

There is growing interest in applying glass as an interposer substrate for 2.5D/3D as well as component substrates for radio frequency (RF) applications. The list of important advantages provided by glass in these applications include material properties (e.g. electrical performance, ability to adjust coefficient of thermal expansion (CTE) to improve reliability) as well as the significant opportunities for cost advantages that glass based solutions provide over other approaches. The feasibility of fabricating high quality holes in glass substrates has been demonstrated. While work in hole fabrication continues, additional efforts to demonstrate and mature downstream processing of glass substrates has accelerated. These include hole metallization and redistribution layers (RDL) in both wafer and panel formats, as well as initial characterization and demonstration of reliability. Significant progress in these areas is reported here.

50μm pitch Pb-free micro-bumps by C4NP technology

Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.

C4NP as a High-Volume Manufacturing Method for Fine-Pitch and Lead-Free FlipChip Solder Bumping

More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies are flipchip in package (FCiP) and wafer level chip scale package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC board (PCB). WLCSP devices connect directly onto the board. There are various solder bumping technologies used in volume production. These include electroplating, solder paste printing, evaporation and the direct attach of preformed solder spheres. FCiP demands many small bumps on tight pitch whereas WLCSP typically requires much larger solder bumps. All these established technologies have important limitations for fine pitch bumping especially when it comes to lead-free solder alloys. The most commonly used method of generating fine-pitch solder bumps is by electroplating the solder. This process is difficult to control and costly, especially when it comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to grant exemptions from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry. C4NP (C4-new process) is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as WLCSP bumping applications. This paper provides a summary of manufacturing and reliability results of C4NP bumped high-end logic devices and how they compare to electroplated lead-free solder bumps. It discusses the relevant process equipment technology and the novel requirements to run a HVM (high volume manufacturing) C4NP process. The paper also talks about the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operation at the Hudson Valley Research Park in East Fishkill, NY

Alternative UBM for Lead Free Solder Bumping using C4NP

This paper analyzes two alternative under bump metallurgy (UBM) structures: sputtered TiW/Ni and electroless Ni/immersion Au (ENIG), with and without Pd. Wafers were fabricated with these UBM structures, solder applied with C4NP, and chip level stressing performed to determine the robustness of these alternative stack-ups. Microelectronic packaging continues the migration from wire bond to flip chip first level interconnect (FLI) to meet aggressive requirements for improved electrical performance, reduced size and weight. Analysis of these structures following multiple reflows and thermal cycling is presented.

C4NP Lead Free Solder Bumping and 3D Micro Bumping

Semiconductor packaging continues to migrate from wire bond to flip chip first level interconnect to meet aggressive size, weight and electrical performance requirements. In addition, novel System in Package (SiP) approaches utilizing 3D packaging technologies and fine-pitch chip to chip interconnection schemes require advanced lead-free solder bumping technologies. Today, solder electroplating is commonly employed for wafer bumping, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, from 3D FC to CSP bump dimensions. As the industry migrates to 300 mm wafer processing and lead-free flip chip intercon nect, C4NP is establishing itself as a viable solder bumping alternative. IBM is ramping production in C4NP and shipping bumped lead-free 300 mm wafers. This paper reviews the C4NP process from mold manufacturing to lead free solder transfer onto 300 mm wafers. Technology applications are summarized, including C4 interconnects and three dimensional (3D) integration. This paper reviews C4NP micro bumping results in support of 3D packaging, and early manufacturing yield results from 300 mm wafer development and manufacturing. Lastly, the most recent lead-free reliability data for both 200mum & 150mum C4 pitch for plated BLMstructures is summarized.

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.

Lead Free Micro Bumping - Cost & Yield Challenges

Technology roadmaps for electronic packaging and 3D integration show the continuing trend of increasing input/output connection density between the semiconductor chip and the package or between two different ICs. For FlipChip packaging applications, 150 mum pitch full grid solder bump arrays have already entered production. Bump pitch requirements for 3D applications such as the integration of memory and logic are even tighter. These fine pitch applications exceed the capabilities of traditional wafer bumping processes such as solder screening or ball placement. Controlled Collapse Chip Connection - New Process (C4NP) technology has the ability to produce these very fine pitch connections in a cost effective manner. This paper reviews the latest C4NP data for a 50 mum pitch application. Glass molds were fabricated, filled with solder, inspected, and the solder transferred to a fine pitch wafer. Four molds have been fabricated with cavity top diameters ranging from ~33 to 40 mum., The molds were filled with binary SnAg solder using the mold fill tool, automatically inspected with the mold inspect tool, and wafers were bumped with the solder transfer tool. Characterization of the filled molds and bumped wafers is presented. In addition, the paper also reviews production cost analysis for various UBM stackups and solder bump processes, based on a specifically developed cost model. The Electroless Ni Immersion Au (ENIG) UBM structures in combination with C4NP solder bumping provide a significant cost reduction over alternative structures. C4NP is a unique solder bumping technology developed by IBM which addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300 mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch as well as chip scale package bumping applications. Fine pitch C4NP molds were fabricated by ULCOAT, Japan. Mold fill, inspect and solder transfer was done using the C4NP process at the IBM Hudson Valley Research Park, Hopewell Junction, New York, United States.

C4NP - IBM Manufacturing & Reliability Data for Lead Free Flip Chip Solder Bumping

C4NP (C4-New Process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. The filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300 mm (or smaller) wafer in a single process step without the complexities associated with liquid flux

C4NP - Lead Free Flip Chip Solder Bumping Manufacturing and Reliability Data

To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in package (FCiP) requires many small bumps on tight pitch whereas wafer level chip scale packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production for wafer bumping. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (controlled collapse chip connection new process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes initial reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec

Lead free solder bump manufacturing with IBM's C4NP process

More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies used are flipchip in package (FCiP) and wafer level chip scale package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC board (PCB). WLCSP devices connect directly onto the board. C4NP (C4-new process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as large pitch/large ball WLCSP bumping applications