Dipanwita RoyChowdhury

CryptoScan: A Secured Scan Chain Architecture

Scan based testing is a powerful and popular test technique. However the scan chain can be used by an attacker to decipher the cryptogram. The present paper shows such a side-channel attack on LFSR-based stream ciphers using scan chains. The paper subsequently discusses a strategy to build the scan chains in a tree based pattern with a selfchecking compactor. It has been shown that such a structure prevents such scan based attacks but does not compromise on fault coverage.

Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable

This paper proposes a programmable GF(p) arithmetic unit for elliptic curve cryptography. The proposed unit can perform modular addition, subtraction, multiplication, inversion, and division. A suitable countermeasure against differential power analysis attack and doubling attack is proposed. An elliptic curve scalar multiplication hardware is subsequently designed for the curves defined over GF(p) using two cores of programmable GF(p) arithmetic unit. It performs point doubling and point addition in each iteration concurrently on two cores. The proposed scalar multiplication hardware is implemented on the Xilinx Virtex-2 Pro FPGA platform. The proposed parallel architecture is inherently programmable, memoryless, and resistant against timing and power attacks. It efficiently optimizes area × time per bit value for elliptic curve scalar multiplication.

{\rm GF}(p)

This paper presents a reconfigurable architecture of the Advanced Encryption Standard (AES-Rijndael) cryptosystem. The suggested reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128, 192, 256) of data and key. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. The work develops a FSMD model based controller which is ideal for such iterative implementation of AES. S-boxes here have been implemented using combinational logic over composite field arithmetic which completely eliminates the need of any internal memory. The design has been implemented on Xilinx Vertex XCV1000 and 0.18μ CMOS technology. The performance of the architecture has been compared with existing results in the literature and has been found to be the most compact implementations of the AES algorithm.

Arithmetic Unit

This paper presents a Pairing Crypto Processor (PCP) over Barreto-Naehrig curves (BN curves). The proposed architecture is specifically designed for field programmable gate array (FPGA) platforms. The design of PCP utilizes the efficient implementation of the underlying finite field primitives. The techniques proposed maximize the utilization of in-built features of an FPGA device which significantly improves the performance of the primitives. Extensive parallelism techniques have been proposed to realize a PCP which requires lesser clock cycles than the existing designs. The proposed design is the first reported result on an FPGA platform for 128-bit security. The PCP provides flexibility to choose the curve parameters for pairing computations. The cryptoprocessor needs 1730 k, 1206 k, and 821 k cycles for the computation of Tate, ate, and R-ate pairings, respectively. On a Virtex-4 FPGA device it consumes 52 kSlices at 50MHz and computes the Tate, ate, and R-ate pairings in 34.6 ms, 24.2 ms, and 16.4 ms, respectively, which is comparable to known CMOS implementations.

An area optimized reconfigurable encryptor for AES-Rijndael

This paper is devoted to the design and the physical security of a parallel dual-core flexible cryptoprocessor for computing pairings over Barreto-Naehrig (BN) curves. The proposed design is specifically optimized for field-programmable gate-array (FPGA) platforms. The design explores the in-built features of an FPGA device for achieving an efficient cryptoprocessor for computing 128-bit secure pairings. The work further pinpoints the vulnerability of those pairing computations against side-channel attacks and demonstrates experimentally that power consumptions of such devices can be used to attack these ciphers. Finally, we suggest a suitable countermeasure to overcome the respective weaknesses. The proposed secure cryptoprocessor needs 1 730 000, 1 206 000, and 821 000 cycles for the computation of Tate, ate, and optimal-ate pairings, respectively. The implementation results on a Virtex-6 FPGA device shows that it consumes 23 k Slices and computes the respective pairings in 11.93, 8.32, and 5.66 ms.

High speed flexible pairing cryptoprocessor on FPGA platform

CAR30 is a new stream cipher that uses classical Rule 30 of Cellular Automata (CA) along with a Maximum Length Linear Hybrid CA. This design can be implemented efficiently both in hardware and software. It has a fast initialization algorithm that makes it suitable for small messages. The generic design of the cipher enables to scale up for any length of Key and IV. This paper describes the cipher with 128-bit Key and 120-bit IV and evaluates the security and implementation aspects of it. The main advantages of the proposed cipher are the flexibility of its design, good hardware throughput in comparison with state-of-the-art hardware oriented ciphers like Grain and Trivium and better software speed than the software oriented stream cipher Rabbit.

Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform

The paper proposes construction techniques for group non-linear Cellular Automata (CA) composing smaller non-linear invertible CA with linear group CA. We prove that such a scheme generates machines with state transitions having predictable cyclic properties. We show that with appropriate choice of the rules of the linear CA we may obtain invertible, balanced Boolean mappings with strong non-linearity. Extensive experimental results are provided to support the claims made.

CAR30: A new scalable stream cipher with rule 30

The paper presents an ASIC design for AES-Rijndael cryptosystem in 0.18 /spl mu/ CMOS technology. The memoryless pipelined architecture achieves a speed of 8 Gbps@250 MHz clock. The pipelined architecture can be made to toggle between the encryption and decryption modes without the presence of any dead cycle. The on-chip key scheduling has been made secured against external attacks. The performance has been compared with those of competitive architectures and exhibits its elegance in successfully optimizing the conflicting requirements of high throughput, less area and low power.

Theory of Composing Non-linear Machines with Predictable Cyclic Structures

In this paper, we study several algorithms for batch verification of ECDSA signatures. The first of these algorithms is based upon the naive idea of taking square roots in the underlying field. We also propose two new and efficient algorithms which replace square-root computations by symbolic manipulations. Experiments carried out on NIST prime curves demonstrate a maximum speedup of above six over individual verification if all the signatures in the batch belong to the same signer, and a maximum speedup of about two if the signatures in the batch belong to different signers, both achieved by a fast variant of our second symbolic-manipulation algorithm. In terms of security, all the studied algorithms are equivalent to standard ECDSA* batch verification. These algorithms are practical only for small (≤8) batch sizes. To the best of our knowledge, this is the first reported study on the batch verification of original ECDSA signatures.

An efficient end to end design of Rijndael cryptosystem in 0.18 /spl mu/ CMOS

This paper proposes a novel technique for testing core based system-on-a-chip (SOC), targeting to reduce the test application time as well as the test hardware. The proposed work is to be done in two parts: (i) Core Level and (ii) Interconnect Level. To date, many authors have studied the problem of testing core-based systems, but not much work exists on testing the cores and the interconnects together. Also proposed is an efficient test access design to reduce test cost by minimising test application time. Test access is a major challenge for testing of core-based system-on-a-chip designs. Several issues related to the Test Access Mechanism (TAM) design such as assignment of cores to test buses, optimal number of buses required, distribution of test data bandwidth between several buses have been handled in this paper. In doing so, the testing time has been found to be drastically reduced at the cost of some extra test hardware.