Indranil Sengupta

An adaptive audio watermarking based on the singular value decomposition in the wavelet domain

This paper presents a secure, robust, and blind adaptive audio watermarking algorithm based on singular value decomposition (SVD) in the discrete wavelet transform domain using synchronization code. In our algorithm, a watermark is embedded by applying a quantization-index-modulation process on the singular values in the SVD of the wavelet domain blocks. The watermarked signal is perceptually similar to the original audio signal and gives high quality output. Experimental results show that the hidden watermark data is robust to additive noise, resampling, low-pass filtering, requantization, MP3 compression, cropping, echo addition, and denoising. Performance analysis of the proposed scheme shows low error probability rates. The data embedding rate of the proposed scheme is 45.9 bps. The proposed scheme has high payload and superior performance against MP3 compression compared to the earlier audio watermarking schemes.

A New Audio Watermarking Scheme Based on Singular Value Decomposition and Quantization

In this paper, we propose a new robust and blind audio watermarking algorithm based on singular value decomposition and quantization index modulation. The watermark insertion and extraction methods are based on quantization of the norm of singular values of the blocks. Audio quality evaluation tests show high imperceptibility of the watermark in the audio signal. Simulation results demonstrate that this algorithm is robust against signal-processing and stirmark attacks. The false negative error probability under the proposed scheme is close to zero. Moreover, the proposed algorithm has higher data payload and better performance than the other related audio watermarking schemes available in the literature.

A class of two-dimensional cellular automata and their applications in random pattern testing

A basic framework to characterize the behavior of two-dimensional (2-D) cellular automata (CA) has been proposed. The performance of the regular structure of the 2-D CA has been evaluated for pseudo-random pattern generation. The potential increase in the local neighborhood structure for 2-D CA has led to better randomness of the generated patterns as compared to LFSR and 1-D CA. The quality of the random patterns generated with 2-D CA based built-in-self-test (BIST) structure has been evaluated by comparing the fault coverage on several benchmark circuits. Also a method of synthesizing 2-D CAs to generate patterns of specified length has been reported. The patterns generated can serve as a very good source of random two-dimensional sequences and also variable length parallel pattern generation having virtually nil correlation among the bit patterns.

A Distributed Trust Establishment Scheme for Mobile Ad Hoc Networks

Wireless ad hoc networks have generated much interest, both in research literature and the telecommunication industry. The attractiveness of these networks lies in the fact that unlike other wireless networks, ad hoc networks are self-organized: the hosts constituting the networks can communicate with each other without reliance on centralized or specialized entities such as base stations. As these networks find more application, the need for adequate security mechanism is increasingly becoming important. Trust establishment and management are essential for any security framework of these networks. In this paper, we present a trust establishment scheme for ad hoc networks based on distributed trust model. A trust initiator is introduced only in the system-bootstrapping phase to initiate the protocol. A fully self-organized trust establishment approach is then adopted to handle the dynamic topology of the network and the membership changes of the nodes, while ensuring trust establishment among the nodes with shorter trust chains and very high probability. The simulation results show that our scheme is highly robust and scalable in the dynamic environment of ad hoc networks

An effective group-based key establishment scheme for large-scale wireless sensor networks using bivariate polynomials

Key establishment in sensor networks is a challenging problem because of the resource limitations of the sensors. Due to resource constraints as well as vulnerable to physical capture of the sensor nodes, the traditional public-key routines are not feasible to apply in most sensor network architectures. Several symmetric key establishment mechanisms are proposed in the literature to establish symmetric keys between communicating sensor nodes for their secret communications in a sensor network, but most of them are not scalable. In this paper, we propose a deterministic group-based key pre-distribution scheme based on a hierarchical wireless sensor networks using bivariate polynomials over a finite field. This scheme guarantees that a direct key is always established between any two neighbor sensors in any deployment group. Our proposed scheme also guarantees that no matter how many sensor nodes are compromised, the non-compromised nodes can still communicate with 100% secrecy, i.e., our scheme is always unconditionally secure against node capture attacks. Moreover, it provides significantly better trade-off between communication overhead, network connectivity and security against node capture compared to the existing key pre-distribution schemes. Finally, it also supports dynamic node addition after the initial deployment of the nodes in the network.

Cellular automata-based recursive pseudoexhaustive test pattern generator

This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that the first 2/sup k/ vectors cover all adjacent k-bit spaces exhaustively. It requires substantially less hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization.

Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning

In wavelength routed optical networks, the number of wavelength channels is limited due to several constraints and each wavelength as well as each lightpath support traffic in the Gbps range. On the other hand, the traffic requested by an individual connection is still in the Mbps range. Therefore, to utilize the network resources (such as bandwidth and transceivers) effectively, several low-speed traffic streams have to be efficiently groomed or multiplexed into one or more high-speed lightpaths. The grooming problem of a static demand is considered as an optimization problem. In this work, we have investigated the traffic grooming problem with the objective of maximizing the network throughput for wavelength-routed mesh networks and map this problem to the clique partitioning problem. We have proposed an algorithm to handle general multi-hop static traffic grooming based on the clique partitioning concept. The efficiency of our approach has been established through extensive simulation on different sets of traffic demands with different bandwidth granularities for different network topologies and compared the approach with existing algorithms.

Exploiting negative control lines in the optimization of reversible circuits

The development of approaches for synthesis and optimization of reversible circuits received significant attention in the past. This is partly due to the increasing emphasis on low power design methodologies, and partly motivated by recent works in quantum computation. While most of them relied on a gate library composed of multiple-control Toffoli (MCT) gates with positive control lines, some initial works also exist which additionally incorporate negative control lines. This usually leads to smaller circuits with respect to the number of gates as well as the corresponding quantum costs. However, despite these benefits, negative control lines have hardly been considered in post-synthesis optimization of reversible circuits so far. In this paper, we address this issue. We are presenting an optimization scheme inspired by template matching which explicitly makes use of negative control lines. Experimental evaluations demonstrate that exploiting negative control lines in fact lead to a reduction in the number of gates and the quantum costs by up to 60% and 25%, respectively.

BDD based synthesis of Boolean functions using memristors

Very recently a new passive circuit element called memristor has been extensively investigated by researchers, which can be used for a variety of applications. This two-terminal device having few nanometer dimensions has been experimentally shown to possess both memory and resistor properties. This has also received great attention due to the fact that these devices can very easily be integrated on CMOS subsystems. Most of the logic design works in this context are based on material implication operation which can be very efficiently implemented using memristors. In this paper we propose an efficient realization of 2-to-1 multiplexer using memristors, and hence present a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and then maps the same to memristor implementation.

An area optimized reconfigurable encryptor for AES-Rijndael

This paper presents a reconfigurable architecture of the Advanced Encryption Standard (AES-Rijndael) cryptosystem. The suggested reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128, 192, 256) of data and key. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. The work develops a FSMD model based controller which is ideal for such iterative implementation of AES. S-boxes here have been implemented using combinational logic over composite field arithmetic which completely eliminates the need of any internal memory. The design has been implemented on Xilinx Vertex XCV1000 and 0.18μ CMOS technology. The performance of the architecture has been compared with existing results in the literature and has been found to be the most compact implementations of the AES algorithm.