Monjur Alam

Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks

All elliptic curve cryptographic schemes are based on scalar multiplication of points, and hence its faster computation signifies faster operation. This paper proposes two different parallelization techniques to speedup the GF(p) elliptic curve multiplication in affine coordinates and the corresponding architectures. The proposed implementations are capable of resisting different side channel attacks based on time and power analysis. The 160, 192, 224 and 256 bits implementations of both the architectures have been synthesized and simulated for both FPGA and 0.13@m CMOS ASIC. The final designs have been prototyped on a Xilinx Virtex-4 xc4vlx200-12ff1513 FPGA board and performance analyzes carried out. The experimental result and performance comparison show better throughput of the proposed implementations as compared to existing reported architectures.

An area optimized reconfigurable encryptor for AES-Rijndael

This paper presents a reconfigurable architecture of the Advanced Encryption Standard (AES-Rijndael) cryptosystem. The suggested reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128, 192, 256) of data and key. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. The work develops a FSMD model based controller which is ideal for such iterative implementation of AES. S-boxes here have been implemented using combinational logic over composite field arithmetic which completely eliminates the need of any internal memory. The design has been implemented on Xilinx Vertex XCV1000 and 0.18μ CMOS technology. The performance of the architecture has been compared with existing results in the literature and has been found to be the most compact implementations of the AES algorithm.

Effect of glitches against masked AES S-box implementation and countermeasure

Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES algorithm. It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks. The phenomenon in CMOS circuits responsible for the leakage of masked circuits is known as glitching. Motivated by this fact, the authors analyse the effect of glitches in CMOS circuits against masked implementation of the AES S-box. The authors explicitly demonstrate that glitches do not affect always. There exists a relation between combinational path delay of the circuit and timing difference of input vectors to the circuit, which has a bearance on the amount of information leaked by the masked gates. A balanced masked S-box circuit is proposed where the inputs are synchronised by sequential components. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.

A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography

This paper presents the architecture and FPGA implementation of a robust GF(p) parallel arithmetic unit. The most efficient modular multiplication, inversion and division units greatly reduce the clock cycles requirement for point operations applicable to elliptic curve cryptography. The parallel arithmetic unit helps to achieve a high speed up in cryptographic applications. The architecture can resist the cryptographic timing attack. Integrated input and output interface units provide lower bandwidth requirement to plug in the architecture with automated cryptographic systems. The design exhibits its elegance among competitive architecture with respect to throughput and robustness.

Preventing the Side-Channel Leakage of Masked AES S-Box

Masking of gates is one of the most popular techniques to prevent Differential Power Analysis (DPA) of AES S- Boxes. However due to the presence of glitches in circuits even masked circuits leak side-channel information. Moti- vated by this fact, we proposed a balanced masked multi- plier where the inputs are synchronized either by sequential components or controlled AND logic, that can be a possible solution for preventing DPA attack on masked implementa- tion of AES S-Boxes. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked multiplier against DPA attacks. Keywords: Side Channel Attacks, Masked Multiplier, AES S-box, Differential Power Analysis

Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm

This paper presents a single chip encryp- tor/decryptor core implementation of Advanced Encryption Standard (AES-Rijndael) cryptosystem. The suggested architecture is capable of handling all possible combinations of standard bit lengths (128,192,256) of data and key. The fully rolled inner- pipelined architecture ensures lesser hardware complexity. The architecture does reutilize precomputed blocks, in the sense that the same hardware is shared during encryption and decryption as much as possible. The design has been implemented on Xilinx XCVe1000-8bg560 device. The performance of the architecture has been compared with existing results in the literature and has been found to be the most efficient (throughput/area) implementation of the AES algorithm.

A GF(p) elliptic curve group operator resistant against side channel attacks

This paper deals with FPGA and ASIC implementations of side-channel attack resistant elliptic curve cryptosystems defined over GF(p). The elegance of the design lies in the fact that all operations are performed in binary number system, thus reducing conversion overheads of existing architectures. In our implementation, point addition and point doubling operations are performed in affine coordinates. They are performed using same amount of computation, which provides a secure design against timing and power analysis attacks. Implementation and side-channel analysis results are compared with related existing designs.

Effect of side channel attacks on RSA embedded devices

Public key cryptosystem RSA is computationally secure against all traditional algorithmic attacks. However, their hardware implementations may be insecure against the analysis of its required time and consumed power during specific computations. This paper shows how insecure implementations of RSA leak information related to their secrete key. The timing analysis and simple and differential power analysis on a careless implementation may help to break a secure cryptosystem. The paper carries some experimental results on RSA exponentiation that specifies how different types of side channel analysis can be performed to break the secure RSA algorithm in its hardware implementation. The paper also significantly gives different countermeasures to overcome specific side channel attacks on RSA exponentiation algorithm.