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Dive into the research topics where Dirk A. Reese is active.

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Featured researches published by Dirk A. Reese.


custom integrated circuits conference | 1995

A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability

Rakesh H. Patel; Myron W. Wong; John Costello; Dirk A. Reese; Vincent T. Bocchino; Michael Chu; John E. Turner

This paper discusses a complex programmable logic device which provides up to 12,000 usable gates. The EPM9560 is the first member of the third-generation MAX 9000 family. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 560 product term based macrocells and circuit techniques to achieve an overall 90.7 MHz system operating frequency. The device is designed to operate in a 3.3 V or 5 V systems. It has built-in JTAG boundary scan for improving testability and in-system programmability for ease of manufacturing.


custom integrated circuits conference | 1998

A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability

Dirk A. Reese; Eric F. H. Chun; Sammy Cheung; Edmond Lau; Michael Chu; Gwen Liang; Nghia Tran; Brad Vest; Richard G. Smolen; Minchang Liang; Seshan Sekariapuram; Behzad Nouban; Myron W. Wong; John Costello; John E. Turner

The methods and circuits used in the design of a high density, high performance, power efficient, complex PLD are discussed. The EPM9560A is the first member of the third generation MAX 9000 family. Developed on a 0.5 /spl mu/m triple layer metal process, significant improvements in die size, performance, and power have been achieved over the previous generations. Circuit enhancements and design methodologies resulting in better performance are discussed. Analysis methods used in the design of a 560 macrocell PLD with a die size of 99.9 Kmil/sup 2/ and a propagation delay under 7 ns are also discussed.


custom integrated circuits conference | 1993

A 10 ns, 4000 gate, 160 pin CMOS EPLD developed on a 0.8 /spl mu/m process

Rakesh H. Patel; Myrong Wong; Dirk A. Reese; John Costello; John E. Turner

The 160-pin EPM7192, an erasable programmable logic device (EPLD) with a system operating frequency in excess of 100 MHz, is described. This 192 macrocell device is the fastest EPLD at this logic density. The input to output propagation delay for this device was measured to be 9.8 ns. The clock to output propagation delay was clocked at 4 ns. This device uses a combination of architectural, process, and circuit improvements to achieve high performance and logic densities. The EPM7192 is implemented on a 0.8-/spl mu/m CMOS-EEPROM (electrically erasable programmable read-only memory) technology.


Archive | 2005

Method for implementing electro-static discharge protection in silicon-on-insulator devices

Dirk A. Reese; Peter J. McElheny; Minchang Liang


Archive | 1998

Method and circuit for reducing output ground and power bounce noise

William Bradley Vest; Dirk A. Reese; Myron W. Wong; John Costello


Archive | 1996

Sense amplifier with individually optimized high and low power modes

Dirk A. Reese; Myron W. Wong; John Costello


Archive | 2008

Techniques for configuring programmable logic using on-chip nonvolatile memory

Thomas H. White; William Bradley Vest; Dirk A. Reese; Myron W. Wong


Archive | 2004

Over-voltage protection of integrated circuit I/O pins

Dirk A. Reese; Tzung-Chin Chang; Chiakang Sung; Khai Nguyen; Gopinath Rangan; Xiaobao Wang


Archive | 1994

Sense amplifier with feedback and stabilization

Myron W. Wong; Dirk A. Reese; John Costello


Archive | 2012

Partial reconfiguration circuitry

Balaji Margabandu; Dirk A. Reese; Leo Min Maung; Ninh D. Ngo

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