Myron W. Wong

A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability

This paper discusses a complex programmable logic device which provides up to 12,000 usable gates. The EPM9560 is the first member of the third-generation MAX 9000 family. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 560 product term based macrocells and circuit techniques to achieve an overall 90.7 MHz system operating frequency. The device is designed to operate in a 3.3 V or 5 V systems. It has built-in JTAG boundary scan for improving testability and in-system programmability for ease of manufacturing.

Cyclone /spl trade/: a low-cost, high-performance FPGA

This paper describes the Altera Cyclone/spl trade/ FPGA, an architecture specifically designed for low-cost, high-volume applications. An optimized routing architecture, simplified I/O structure, and carefully selected features combine to yield a 57% die size reduction relative to a Stratix/spl trade/ device of similar logic density, with a 7% reduction in performance.

A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming

A high density, Programmable Logic Device (PLD) family developed for hot socketing and high performance is discussed. The family is fabricated on a 0.32 um quadruple layer metal process. The largest family member is a 512 macrocell part with typical pin to pin delays of 4.9 ns. The design techniques and testing methodology to guarantee safe hot socketing are described. Streamlined In System Programming (ISP) and circuits used to configure EEPROM cells with a 3.3-V supply are also discussed.

A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability

The methods and circuits used in the design of a high density, high performance, power efficient, complex PLD are discussed. The EPM9560A is the first member of the third generation MAX 9000 family. Developed on a 0.5 /spl mu/m triple layer metal process, significant improvements in die size, performance, and power have been achieved over the previous generations. Circuit enhancements and design methodologies resulting in better performance are discussed. Analysis methods used in the design of a 560 macrocell PLD with a die size of 99.9 Kmil/sup 2/ and a propagation delay under 7 ns are also discussed.

A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability

A high density programmable logic device (PLD) specifically developed for high performance and for ease of use in production flows is presented. This device is designed on a 0.5 /spl mu/m triple layer metal process to produce a 55 kmil/sup 2/ die size and with the built-in frequency multiplier, allows system performance of up to 140 MHz to be achieved.