Dirk Bormann

A 1.3 V, 65nm CMOS, coilless combined feedback LNA with integrated single coil notch filter

An LNA with integrated notch filter is demonstrated. It consists of a coilless two-stage LNA with capacitive feedback and an integrated Q-enhanced notch filter. Thus, this circuit is capable for use in FDD systems like UMTS or WCDMA without additional off-chip interstage filter, especially for highly integrated multi-band multi-standard transceivers as only one area consuming coil is used.

Design of frequency agile filters in RF frontend circuits

Frequency agile filter are key components for future cognitive radio applications. Bandpass filters based on the principle of lowpass upconversion allow simple and CMOS-friendly solutions to cognitive radio filter problems. Because the center frequency depends on the LO-frequency only, the band selection is adjusted with the receive mixers LO simultaneously. A frequency agile filter has been incorporated into a 600 MHz to 800 MHz wideband LNA with a gain of 18 dB at 700 MHz. It consumes 8.7 mA from a 1.4 V supply. With a 3 dB-bandwidth of 14 MHz, the filter achieves a selectivity of 9.5 dB at 40 MHz frequency offset. Measurement results of a prototype chip in 90 nm CMOS prove the presented theory.

A frequency agile LNA for cognitive radio applications in the UHF band

A frequency selective LNA for the UHF band is presented that uses an N-Path filtering concept to realize frequency agile filtering between 600 MHz and 800 MHz. A frequency generator like an on-chip PLL can be used to choose the filter band without the need for an additional post-production calibration step. The LNA concept uses the advantages of the source degenerated as well as the shunt feedback LNA. The characteristic of the LNA and the filter function is described in detail. Measurement results from a prototype chip in 90 nm CMOS prove the presented theory. At 700 MHz the LNA offers a gain of 18dB without filtering and 17dB with filtering applied. The noise figure is as low as 3.1dB and increases to 3.9dB with filtering. The linearity in terms of the intermodulation point IP3 is as high as 0 dBm. A single filter gives 9.5 dB selectivity at 40MHz frequency offset. Using only a source inductor, the LNA area occupation is lower than 0.2 mm2.

A Variable Gain Multiband Shunt Feedback LNA for LTE

The future belongs to multiband bandwidth-on-demand mobile networks. Simply reconfigurable mobile devices will be the key to handle the increasing number of bands as well as the varying bandwidth requirements. The LNA constitutes the first block of the receiver chain and therefore has to implement the highest level of reconfigurability. A shunt feedback LNA has been designed that can be used for multiple frequency bands. The proposed LNA has two gain steps incorporating a wideband match of at least −10 dB. Below 2 GHz the minimum gain is above 26 dB and the noise figure is below 1.9 dB. Below 1 GHz the gain is above 30 dB and the noise figure is below 1.5 dB. The IIP3 in low gain mode is least 5.8 dBm. The results have been obtained using a current of 8.7mA from a 1.4V supply in a 90 nm CMOS technology.

A comparison of bandwidth setting concepts for Q-enhanced LC-tanks in deep-sub micron CMOS processes

In this paper LC-resonator bandwidth setting techniques in deep-sub micron CMOS processes are examined and compared with the main focus on Q-enhancement, linearity, noise, power consumption and controllability at low supply voltages. Simulations have been performed using an ideal amplifier model to achieve results independent of the purpose of the circuit. The Q-enhancement is achieved by positive feedback into the gates of a cross coupled MOSFET transistor pair. The different Q-tuning concepts include current control techniques as well as capacitive subdivision in the feedback path. As result of this work, a combination of tail current controlled and capacitive subdivision has been found to be the best mean to achieve highest linearity at good controllability. Simulation results show that a quality factor around 100 is possible at a current consumption of maximum 3 mA. The equivalent input noise does not exceed 1.5 nV/radic(Hz) with total harmonic distortion around 0.005% which makes the circuit reasonable for application in LNAs as well as for transmitter structures.

A fully integrated Q-enhanced notch filter LNA for TX blocker suppression in FDD systems

An LNA with integrated Q-enhanced notch filter for use in FDD transceiver systems has been demonstrated. The amplifier core is coilless, made possible by the use of capacitive shunt-series feedback to simplify matching. Additionally, a Q-enhanced notch filter is integrated which attenuates TX blockers thus making an external interstage SAW filter redundant. A prototype was produced on a 65nm CMOS process. Without filter operation it draws 16.6mA from a 1.3V supply, with filter switched on the Q-enhancement adds 2.3–4.1 mA, depending on the demanded selectivity. The filter can be disconnected from the LNA. At 100 Ω source impedance the input reflection factor S11 does not exceed −15 dB for the chosen frequency. The tuning range of the filter is 1500–1780 MHz for RX. The LNA supplies 24.5dB gain with a noise figure of NF = 2.3 dB. For 9 dB selectivity, the gain at RX drops to 20dB and the NF increases to 4.1 dB. The point where the RX gain drops 1dB due to a TX blocker is increased from −23.3 dBm to −19.5 dBm thus showing a proof-of-concept.

A novel notch filter LNA for use in multi-band, multi-standard cellular receivers

A novel LNA with integrated notch filter for multi-band, multi-standard cellular communication is presented in this paper. The LNA is capable to serve multiple FDD bands of the LTE standard and its cobanded UMTS counterparts. Due to its architecture also TDD bands including GSM bands DCS1900 and PCS1800 and LTE TDD bands can be covered. Due to the integrated notch filter which is reused for all covered bands external interstage filters can be omitted thus saving PCB area and component costs. Exemplary for LTE band II, simulations reveal a noise figure of 1.96 dB at 1930 MHz and 10.3 dB selectivity at 80 MHz duplex distance. The inband-IIP3 reaches -10.27 dBm, while IIP3DPX = -10.4 dBm and IIP3HDPX = -2.6 dBm. The circuit works from a 1.4 V supply, drawing 15.3 mA on a commercial 90 nm process.

3.5 GHz triple cascaded current-reuse low noise amplifier

A triple cascaded current-reuse CMOS low noise amplifier (LNA) for 3.5 GHz WiMAX application is presented. Three common-source amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. To achieve input and noise matching simultaneously, an additional capacitor is employed to adjust quality factor and reduce the gate induced current noise. The measurement results show a maximum power gain of 21.7 dB and minimum noise figure of 3.11 dB. The power consumption is 5.16 mW. The chip including pads occupies 1.05 mm × 0.93 mm. A figure-of-merit of 49.7 is reached.