Muh-Dey Wei

A 2.4-GHz low power high performance frequency synthesizer based on current-reuse VCO and symmetric charge pump

This paper presents a low power high performance frequency synthesizer. Based on the current-reuse VCO architecture, the whole system power consumption is significantly saved with excellent phase noise performance. Imbalance amplitude problems caused by the unsymmetrical VCO are solved by the pre-tuning mechanism, which automatically chooses the correct frequency band for the certain frequency channel. Besides, the symmetric charge pump (CP) can minimize the current mismatches and phase offset. The frequency synthesizer is fully integrated in 130-nm CMOS technology consuming 5.8 mW. Measurement results show performance of -130 dBc/Hz at 1 MHz offset phase noise, 450 fs rms jitter. The reference spur is below -75dB, and it operates successfully with 1Mbps GFSK signals as the two-point modulated transmitter.

Investigation of Wideband Load Transformation Networks for Class-E Switching-Mode Power Amplifiers

In this paper, single-ended and differential class-E load transformation networks (LTNs) for wideband operation are investigated. For this purpose, a differential third parallel-tuned tank LTN and a parallel-circuit load LTN without suppressing tanks are proposed to fulfill the class-E wideband condition. The differential parallel-circuit load (DPCL), which considers the finite RF chokes, has higher output resistance, and because of the differential structure, which ensures an open circuit at even harmonic frequencies, it is able to cover a wide frequency range. Consequently, the DPCL is well suited for highly integrated monolithic designs, as well as wideband application. Based on this analysis, a wideband class-E switching-mode power amplifier in CMOS 90 nm using the DPCL is designed. By deliberately combining the LTN with an on-chip balun, a compact size of 1.2 mm2 is achieved. The circuit performance dependency on bond-wire length variation is analyzed and discussed. Measured results show a peak output power of 28.7 dBm, power-added efficiency (PAE) of 48.0%, and drain efficiency of 55.0% at 2.3 GHz. From 1.7 to 2.7 GHz, PAE is higher than 42% and output power is above 25 dBm.

High dynamic-range and sensitivity six-port receiver using reactive matching technique

Six-port receivers have increasingly become popular due to their simple design, wide bandwidth and low power consumption. Large area and narrow dynamic range are the key factors in limiting the use of six-port topology in commercial mobile communication devices. In order to improve its dynamic range, we propose an L-type reactive matching network for the detector stage of the six-port receiver. The proposed six-port receiver covers the frequency band from 1 GHz to 3.3 GHz. Over the specified band, it has an EVM of less than 4 % with -20 dBm of RF input power and 15 dBm of LO power. At 2.2 GHz, it has 64 dB of dynamic range with EVM between 0.33 % and 10.5 %.

Design of frequency agile filters in RF frontend circuits

Frequency agile filter are key components for future cognitive radio applications. Bandpass filters based on the principle of lowpass upconversion allow simple and CMOS-friendly solutions to cognitive radio filter problems. Because the center frequency depends on the LO-frequency only, the band selection is adjusted with the receive mixers LO simultaneously. A frequency agile filter has been incorporated into a 600 MHz to 800 MHz wideband LNA with a gain of 18 dB at 700 MHz. It consumes 8.7 mA from a 1.4 V supply. With a 3 dB-bandwidth of 14 MHz, the filter achieves a selectivity of 9.5 dB at 40 MHz frequency offset. Measurement results of a prototype chip in 90 nm CMOS prove the presented theory.

A frequency agile LNA for cognitive radio applications in the UHF band

A frequency selective LNA for the UHF band is presented that uses an N-Path filtering concept to realize frequency agile filtering between 600 MHz and 800 MHz. A frequency generator like an on-chip PLL can be used to choose the filter band without the need for an additional post-production calibration step. The LNA concept uses the advantages of the source degenerated as well as the shunt feedback LNA. The characteristic of the LNA and the filter function is described in detail. Measurement results from a prototype chip in 90 nm CMOS prove the presented theory. At 700 MHz the LNA offers a gain of 18dB without filtering and 17dB with filtering applied. The noise figure is as low as 3.1dB and increases to 3.9dB with filtering. The linearity in terms of the intermodulation point IP3 is as high as 0 dBm. A single filter gives 9.5 dB selectivity at 40MHz frequency offset. Using only a source inductor, the LNA area occupation is lower than 0.2 mm2.

Investigation of Sub-Milliwatt Current-Reuse VCOs With Mono-Spontaneous Transconductance Match Technique

In this paper, we investigate amplitude compensation techniques of current-reuse (CR) voltage-controlled oscillators (VCOs) and propose an innovative mono-spontaneous transconductance match (m-STM) compensation technique. Due to the asymmetrical structure of CR VCOs, the imbalance between two differential oscillating amplitudes is inevitable. The proposed m-STM technique is able to overcome the unpredictable amplitude imbalance. Compared to a typical spontaneous transconductance match technique, the m-STM consumes less voltage headroom and is thus suitable for low-voltage application. Two sub-Milliwatt VCOs are designed and implemented. The first VCO, using the m-STM technique, demonstrates the compensation of amplitude oscillation and the feasibility of a lower supply voltage. The measured imbalance ratio is less than 0.8%. The power consumption is 0.9 mW using a supply voltage of 1.0 V. A FOM T of -191.6 dBc/Hz is achieved. The second VCO is designed for ultra-low-power consumption. The power consumption is less than 0.4 mW using a supply voltage of 0.9 V and the imbalance ratio is below 4.6%. A FOMT of -193.1 dBc/Hz is achieved.

Impact of modulation order and DAC resolution on high data rate wireless transmitters

Although the speed of a digital-to-analog converter (DAC) can reach 100GS/s in recent studies, the achievable effective number of bit (ENOB) is still significantly low. The low ENOB limits the high speed DAC application in high-data-rate transmitters. This paper analyses the required DAC resolution for different modulation orders, which is determined by error vector magnitude (EVM). To verify the output, a high-data-rate quadrature-amplitude-modulation (QAM) transmitter is modeled. Each block is modeled in Verilog/Verilog AMS. According to the model, a data-rate of 20 Gb/s transmitter with 16-QAM and 7 bit DAC is simulated. Even if taken phase error of 5 degree and gain mismatch of 1.3 dB into account, the model works properly. Adjacent channel leakage ratio (ACLR), at 1-dB compression point of 35 dBm, reduced from -29.5 dBc to -23.3 dBc.

Wideband six-port receiver using elliptical microstrip-slot directional couplers

A prototype of a wideband six-port receiver is presented. It consists of three multilayer elliptical microstrip-slot directional couplers (MSDCs), a power divider and reactive-matching power detectors. To compose the receiver using MSDCs, a controlled-impedance via is required. The via, taken advantage of the multilayer structure, reaches a bandwidth of more than 190% and low insertion loss. 64-QAM signals with different data rates are fed for testing. From 0.5 GHz to 5 GHz the measured EVM is less than 4% with 1 Mbps data rate. The operation frequency covers many commercial standards and thus, the concept is suitable for cognitive radio application. A sensitivity of -52dBm and -58dBm is achieved at 0.9 GHz and 2.4 GHz, respectively, without LNAs.

Highly linear and reliable low band class-O RF power amplifier in 130 nm CMOS technology for 4G LTE applications

This paper presents a highly linear low-band 706MHz LTE compatible class-O RF power amplifier in 130nm CMOS technology for handheld wireless applications. Class-O topology uses a combination of common-source and common-drain amplifiers working in parallel with high linearity without the need for digital predistortion(DPD). With continuous wave measurements, 1-dB compression point (P1dB) of 30.6dBm and peak power added efficiency (PAE) of 45.2% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an ACPR less than -30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common-source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst VSWR conditions.

Wideband, high data-rate, six-port direct-conversion receiver with improved output matching and sensitivity

A wideband, six-port, direct-conversion receiver operating between 0.9 GHz and 5 GHz is presented. It employs distributed power detectors that achieve good matching up to 4 GHz and more than twice the sensitivity as compared to a resistive-matching detector. Comparison of the proposed receiver to one employing resistive-matching detectors, is also presented. The proposed design is able to deliver comparably higher data-rates for a given EVM. Alternately, it provides better EVM for the same data-rate. Measurement results demonstrate the successful demodulation of a 200 Mbps, 16 QAM signal operating at a carrier-frequency of 2.4 GHz.