Dirk Brown

Cluster interactions and stress evolution during electromigration in confined metal interconnects

In narrow metal interconnects used in advanced integrated circuits, electromigration flux divergences occur at the intersection between polycrystalline cluster segments (where grain boundaries offer a fast diffusion path), and bamboo segments (where there are no grain boundaries along the line length). In confined, passivated metal interconnects, these flux divergences are linked to the evolution of significant mechanical stresses in the metal. A quasisteady state stress distribution builds up quickly in the cluster segments and remains unchanged until the stress profiles between cluster segments begin to overlap, and the clusters begin to ‘‘interact.’’ A significant increase in stress above the quasisteady state can result from cluster interactions, increasing the potential for electromigration and stress‐induced damage. If the cluster separation is small, this stress increase can occur on a time scale which is short compared to the stress evolution of the interconnect line as a whole.

The Effect of Cluster Interactions on Electromigration Induced Stress Evolution in Confined Metal Lines

In near-bamboo interconnect lines used in advanced integrated circuits, electromigration flux divergences occur at the intersection between polycrystalline cluster segments (where grain boundaries offer a fast diffusion path), and bamboo segments (where there are no grain boundaries along the line length). For confined, passivated metal interconnects, these flux divergences are linked to the evolution of significant mechanical stresses in the metal. A quasisteady state stress distribution builds up relatively quickly in the cluster segments and remains unchanged until there is significant diffusion into the bamboo segments. The stress profile of a given cluster then becomes dependent on neighboring clusters as well as the diffusivity and flux in the separating bamboo segments. Previous analyses of electromigration failure in interconnect lines have focused on the distribution of cluster lengths and the stress build up in isolated cluster segments. In this paper, we show that the bamboo length distribution can strongly affect the interaction between clusters and the evolution of stresses in a near-bamboo interconnect during electromigration. We present simulation results, using a ratio of cluster to bamboo diffusivity Dc/Db=100, which show greater interactions and larger maximum stresses in cluster segments as the average bamboo segment length decreases and as the bamboo segment length distribution widens.

Effect of CU and SI in Aluminum on Stress Change and on TiAl 3 Formation in Al Alloy/TI Bilayer Films During Annealing

Interconnect metallizations used in advanced integrated circuits typically use an Al-alloy sputterdeposited onto a Ti barrier layer. The Ti and Al react above ∼ 400°C to form TiAl 3 , which affects the stress evolution of the metal stack during thermal cycling. This paper describes results of thin film experiments performed on Ti/Al-alloy bilayer films. Two Al alloys were studied: Al-I%Cu and Al-0.5%Cu-1%Si. The rate of TiAl 3 formation at 430°C was determined for both alloys and used to relate TiAl 3 formation to the stress evolution of the film stacks during thermal cycling. The dominant effect of the TiAl 3 intermetallic formation on stress arises from a change in the stress-temperature behavior of the film stack, due to a change in the yield behavior, effective modulus, and thermal expansion coefficient of the stack. The presence of Si in the Al-alloy markedly reduces both the rate of TiAl 3 formation and the resulting change in composite stress.

A low temperature integrated aluminum metallization technology for ULSI devices

Abstract An integrated aluminum metallization process (Cool Al technology) was successfully applied to fabricate device wafers for the 0.25-μm technology. This new technology integrates CVD and PVD aluminum thin film deposition processes into a high vacuum cluster tool, the applied materials’ Endura, and is capable of reliable contact and via fills of high aspect ratio (>8:1) structures at low temperatures, typically around 330–400°C. Two different Cool Al integration sequences employing CVD TiN and Ti as liners were used to process device wafers with 0.3 and 0.4×1.2μm via structures. The fill performance and electrical and reliability characteristics of the devices were evaluated. Void-free fills of all via structures were achieved. In comparison with a standard W-plug process, both Cool Al splits show more than five times reduction in via resistance. The two Cool Al sequences yielded excellent electromigration (EM) reliability, equivalent or better than a standard W-plug process. Interestingly, the two Cool Al splits, with very different aluminum crystal textures, resulted in similar EM performance.

IMP Ta/Cu seed layer technology for high-aspect-ratio via fill by electroplating, and its application to multilevel single-damascene copper interconnects

Filling of high aspect ratio vias with electroplated copper requires smooth and continuous seed layer whereas prevention of copper diffusion into the adjacent dielectric requires adequate coverage of the barrier along the via sidewalls. Conventional PVD DC magnetron techniques were found to be inadequate for this application, because of insufficient step coverage especially that of Cu on the sidewalls of the high aspect ratio vias, and its agglomeration into discontinuous islands. Ionized metal plasma (IMP) based PVD technology provided superior step coverage of Ta and Cu because of the directionality of the deposited atoms and utilization of ion bombardment to sputter material from the bottom of the via to the sidewalls, thus yielding continuous and conformal barrier and seed layers. Furthermore, the seed layer morphology especially the roughness of the film on the sidewall was found to be quite sensitive to the deposition temperature. The seed layer thickness and film morphology, as well as other deposition parameters as the ratio of coil RF & target DC plasma powers, Ar sputtering pressure, wafer bias and the Ar sputter etch prior to barrier deposition, were all found to affect the subsequent via filling by electroplating. Optimization of the processes enabled filling of high aspect ratio vias. Manufacturability and the process window for the barrier/seed layer processes was evaluated by extended runs and DOEs. The technology was successfully integrated into a multilevel interconnect scheme utilizing Cu plugs, and Cu damascene lines. The via resistance of the Cu plug using this metallization scheme, was found to be significantly lower than that of W plug currently used for Al interconnects. The cost of ownership (COO) of the IMP Ta/Cu seed layer was determined to be significantly lower compared to the current state-of- the-art IMP Ti/CVD TiN liner for W plug.

Dependence of electromigration failure modes on EM-induced and thermally-induced mechanical stress in interconnect lines

Experimental verification of electromigration failure modes on the mechanical stress state of interconnects line during accelerated EM tests is presented in this paper. The electromigration failure mode and failure rate during accelerated electromigration testing is expected to be strongly affected by the mechanical stress state of Al lines, since tensile stress and compressive stress states favor void growth and hillock formations, respectively. During electromigration testing, the mechanical stress state or evolution of mechanical stress of an interconnect is a function of current density and temperature, the two principal variables in electromigration testing. In our experiments, we have observed two different electromigration failure modes by varying the current density and temperatures where (i) the passivated Al lines tested at high current density and high temperatures failed by hillock type failure and (ii) the interconnect lines tested at low current density and moderate temperatures failed by vo...

Effect of Mechanical Stress on Electromigration Failure Mode During Accelerated Electromigration Tests

The electromigration failure mode and failure rate during accelerated electromigration testing is expected to be strongly affected by the mechanical stress state of Al lines, since tensile stress and compressive stress states favor void growth and hillock formations (extrusions), respectively. During electromigration testing, the mechanical stress state or evolution of mechanical stress of an interconnect is a function of current density and temperature, the two principal variables in electromigration testing. In our experiments, we have observed two different electromigration failure modes by varying the current density and temperatures where (i) the passivated Al lines tested at high current density and high temperatures failed by extrusion or hillock type failure and (ii) the interconnect lines tested at low current density and moderate temperature failed by voiding. A mechanical stress model which incorporates both the thermally generated stress and electromigration induced mechanical stress is invoked to explain the electromigration failure mode selection observed in our experiments.