Van Pham

The effect of low-k ILD on the electromigration reliability of Cu interconnects with different line lengths

We have compared the electromigration performance of Cu electromigration structures with varying line lengths imbedded in two different ILD materials. In the regime of high jL where there is no significant back-stress, we observed that three of the key electromigration parameters (i.e., MTF, n, and /spl sigma/) are constant and approximately equivalent between the two materials. In the regime of lower jL where there is significant back-stress, both materials exhibit similar trends, however, the Cu with low-k material performed relatively worse in terms of MTF and similarly in terms of n and /spl sigma/. That is, while the MTF of Cu with both materials increased with decreasing jL, the MTF of Cu with low-k material was less than that of the Cu with SiO/sub 2/-based material due to lower back-stress at a given jL. Further, while a regime of complete immortality was observed for the SiO/sub 2/-based material, no regime of immortality was observed for the low-k material. The values of n and /spl sigma/ were comparable for both materials, and were constant in the absence of significant back-stress but increased in the presence of significant back-stress. Due to the higher MTFs in the regime of high backstress, MTF is more sensitive to j and L, thereby increasing n as per Blacks Law. The increase in /spl sigma/ is a consequence of heightened sensitivity to process variations such as via barrier integrity and CD variation.

Electromigration of C4 bumps in ceramic and organic flip-chip packages

As technology continues to scale, there is increasing demands on I/O counts and power requirements, leading to decreasing solder pitch and increasing current density for solder bumps in high-density flip-chip packages. At the same time, increasing performance requirements has led to the use of organic packages instead of the conventional ceramic packages. Hence it is very important to be able to measure the current carrying capability of solder bumps and evaluate the impact of reduced bump pitch and use of organic packages on EM reliability. In this paper, we run conventional EM test configuration using mechanically shorted dies and making the connection to the solder bumps through the flip-chip package directly mounted on the test boards to evaluate the effect of varying bump pitches on the electromigration performance of the solder bumps. Our results show that electromigration resistance is very high on ceramic packages with high lead solders and degrades significantly when high lead solder is used in conjunction with eutectic solder on organic packages

A via failure mode in electromigration of multilevel interconnect

Via electromigration (EM) performance of (Al-1% Si-0.5% Cu)/(Ti/TiN/Al-1% Si-0.5% Cu) metallization systems has been evaluated for vias with sizes ranging from 1 mu m to 2 mu m. The electrical open failure mode for vias was observed during EM test at high temperatures and with different current densities. The activation energy and current exponent were obtained, suggesting surface and lattice diffusion as the probable failure mechanisms. A novel observation from this study was the self-healing of failed vias when the failed chains were stored at room or high temperatures. A model for the failure mechanism is proposed.<<ETX>>

Wheatstone bridge method for electromigration study of solder balls in flip-chip packages

In this paper, we describe a new approach and a new system developed for EM tests of solder balls in a packaging assembly. The approach was based on the Wheatstone bridge method, which provided significant improvement in the sensitivity for detecting EM damage in solder balls. In the bridge circuit, each of the arms can contain an ensemble of solder balls connected in series and/or in parallel to increase the number of solder balls being tested. Thus the method can be used for EM tests of a large ensemble of solder balls, extending the range of statistical detection of early failures and reducing EM test time. Using this method, EM tests were performed at 165/spl deg/ and 235/spl deg/C on 97Pb-3Sn solder balls in ceramic flip-chip packages. The results yielded an activation energy of 0.85 eV. By extending the test time to 2000 hrs at 165/spl deg/C, all of the test circuits except one showed resistance saturation, suggesting the existence of a threshold jL/sub c/ product. Subjected to a maximum resistance change of about 15 m/spl Omega/, the jL/sub c/ product was estimated to be 110 A-cm for 97Pb-3Sn solders at 165/spl deg/C.

Isothermal test as a WLR monitor for Cu interconnects

The need for higher interconnect current densities has been increasing rapidly for advanced integrated circuits. Cu interconnects have emerged as viable candidates to replace Aluminium due to the lower sheet resistivity and increased electro migration lifetime of Cu. Previously, we had reported the use of the isothermal test as a WLR monitor for detecting process defects such as voids in the Aluminium interconnects. This paper further extends the application of the isothermal test methodology for detecting and characterizing process defects in Cu interconnect technology. Package electro migration test are time consuming and may be impractical in detecting process defects in a timely manner. Isothermal test, on the other hand, can be effectively used as a fast WLR process monitor. This paper reports the influence of direction of test current as well as different types of test structures, such as a single level NIST structure and a via chain structure and a via chain structure, on the isothermal test results for Cu interconnects. The isothermal test data has been shown to be helpful in evaluating the location and severity of the process defects through a proper choice of test structures. Joule heating due to high current density is found to be the major driving force for the sensitivity of isothermal test failures. A good correlation is also seen with the package electro migration data. A simple wafer level isothermal test has thus been successfully demonstrated as a reliability tool for process monitoring in Cu VLSI interconnects.

Dependence of electromigration failure modes on EM-induced and thermally-induced mechanical stress in interconnect lines

Experimental verification of electromigration failure modes on the mechanical stress state of interconnects line during accelerated EM tests is presented in this paper. The electromigration failure mode and failure rate during accelerated electromigration testing is expected to be strongly affected by the mechanical stress state of Al lines, since tensile stress and compressive stress states favor void growth and hillock formations, respectively. During electromigration testing, the mechanical stress state or evolution of mechanical stress of an interconnect is a function of current density and temperature, the two principal variables in electromigration testing. In our experiments, we have observed two different electromigration failure modes by varying the current density and temperatures where (i) the passivated Al lines tested at high current density and high temperatures failed by hillock type failure and (ii) the interconnect lines tested at low current density and moderate temperatures failed by vo...

Fast and accurate isothermal measurements on process-split wafers

The tremendous push for high Performance integrated circuits requires short process development cycle. Rapid reliability assessments on interconnect process technology is becoming increasingly indispensable. WLR isothermal test is a fast and effective tool to monitor process-induced defects in VLSl Cu interconnects. It shows good correlation with standard package electromigration tests. A new methodology is introduced to improve the accuracy and testing time of isothermal testings on multi-process splits.

Effect of Mechanical Stress on Electromigration Failure Mode During Accelerated Electromigration Tests

The electromigration failure mode and failure rate during accelerated electromigration testing is expected to be strongly affected by the mechanical stress state of Al lines, since tensile stress and compressive stress states favor void growth and hillock formations (extrusions), respectively. During electromigration testing, the mechanical stress state or evolution of mechanical stress of an interconnect is a function of current density and temperature, the two principal variables in electromigration testing. In our experiments, we have observed two different electromigration failure modes by varying the current density and temperatures where (i) the passivated Al lines tested at high current density and high temperatures failed by extrusion or hillock type failure and (ii) the interconnect lines tested at low current density and moderate temperature failed by voiding. A mechanical stress model which incorporates both the thermally generated stress and electromigration induced mechanical stress is invoked to explain the electromigration failure mode selection observed in our experiments.